Re: [PATCH v8 0/4] perf: arm-spe: Decode SPE source and use for perf c2c

From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Ali Saidi <alisaidi@amazon.com>, Joe Mario <jmario@redhat.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, german.gomez@arm.com,
	leo.yan@linaro.org, benh@kernel.crashing.org,
	Nick.Forrington@arm.com, alexander.shishkin@linux.intel.com,
	andrew.kilroy@arm.com, james.clark@arm.com,
	john.garry@huawei.com, Jiri Olsa <jolsa@kernel.org>,
	kjain@linux.ibm.com, lihuafei1@huawei.com, mark.rutland@arm.com,
	mathieu.poirier@linaro.org, mingo@redhat.com,
	namhyung@kernel.org, peterz@infradead.org, will@kernel.org
Subject: Re: [PATCH v8 0/4] perf: arm-spe: Decode SPE source and use for perf c2c
Date: Tue, 17 May 2022 18:20:03 -0300	[thread overview]
Message-ID: <YoQRg1r7HuwiO3bZ@kernel.org> (raw)
In-Reply-To: <20220517020326.18580-1-alisaidi@amazon.com>

Em Tue, May 17, 2022 at 02:03:21AM +0000, Ali Saidi escreveu:
> When synthesizing data from SPE, augment the type with source information
> for Arm Neoverse cores so we can detect situtions like cache line
> contention and transfers on Arm platforms. 
> 
> This changes enables future changes to c2c on a system with SPE where lines that
> are shared among multiple cores show up in perf c2c output. 
> 
> Changes is v9:
>  * Change reporting of remote socket data which should make Leo's upcomping
>    patch set for c2c make sense on multi-socket platforms  

Hey,

	Joe Mario, who is one of 'perf c2c' authors asked me about some
git tree he could clone from for both building the kernel and
tools/perf/ so that he could do tests, can you please provide that?

thanks!

- Arnaldo

> Changes in v8:
>  * Report NA for both mem_lvl and mem_lvl_num for stores where we have no
>    information
> 
> Changes in v7:
>  * Minor change requested by Leo Yan
> 
> Changes in v6:
>   * Drop changes to c2c command which will come from Leo Yan
> 
> Changes in v5:
>   * Add a new snooping type to disambiguate cache-to-cache transfers where
>     we don't know if the data is clean or dirty.
>   * Set snoop flags on all the data-source cases
>   * Special case stores as we have no information on them
> 
> Changes in v4:
>   * Bring-in the kernel's arch/arm64/include/asm/cputype.h into tools/ 
>   * Add neoverse-v1 to the neoverse cores list
> 
> Ali Saidi (4):
>   tools: arm64: Import cputype.h
>   perf arm-spe: Use SPE data source for neoverse cores
>   perf mem: Support mem_lvl_num in c2c command
>   perf mem: Support HITM for when mem_lvl_num is any
> 
>  tools/arch/arm64/include/asm/cputype.h        | 258 ++++++++++++++++++
>  .../util/arm-spe-decoder/arm-spe-decoder.c    |   1 +
>  .../util/arm-spe-decoder/arm-spe-decoder.h    |  12 +
>  tools/perf/util/arm-spe.c                     | 110 +++++++-
>  tools/perf/util/mem-events.c                  |  20 +-
>  5 files changed, 383 insertions(+), 18 deletions(-)
>  create mode 100644 tools/arch/arm64/include/asm/cputype.h
> 
> -- 
> 2.32.0

-- 

- Arnaldo