From: Bagas Sanjaya <bagasdotme@gmail.com>
To: Huacai Chen <chenhuacai@loongson.cn>
Cc: Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>, Jonathan Corbet <corbet@lwn.net>,
Linus Torvalds <torvalds@linux-foundation.org>,
linux-arch@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>,
Yanteng Si <siyanteng@loongson.cn>,
Huacai Chen <chenhuacai@gmail.com>, Guo Ren <guoren@kernel.org>,
Xuerui Wang <kernel@xen0n.name>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Stephen Rothwell <sfr@canb.auug.org.au>,
WANG Xuerui <git@xen0n.name>
Subject: Re: [PATCH V14 03/24] Documentation: LoongArch: Add basic documentations
Date: Fri, 3 Jun 2022 08:45:18 +0700 [thread overview]
Message-ID: <YplnruNz++gABlU0@debian.me> (raw)
In-Reply-To: <20220602115141.3962749-4-chenhuacai@loongson.cn>
On Thu, Jun 02, 2022 at 07:51:20PM +0800, Huacai Chen wrote:
> +Legacy IRQ model
> +================
> +
> +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
> +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
> +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
> +to LIOINTC, and then CPUINTC.
> +
> + +---------------------------------------------+
> + |:: |
> + | |
> + | +-----+ +---------+ +-------+ |
> + | | IPI | --> | CPUINTC | <-- | Timer | |
> + | +-----+ +---------+ +-------+ |
> + | ^ |
> + | | |
> + | +---------+ +-------+ |
> + | | LIOINTC | <-- | UARTs | |
> + | +---------+ +-------+ |
> + | ^ |
> + | | |
> + | +-----------+ |
> + | | HTVECINTC | |
> + | +-----------+ |
> + | ^ ^ |
> + | | | |
> + | +---------+ +---------+ |
> + | | PCH-PIC | | PCH-MSI | |
> + | +---------+ +---------+ |
> + | ^ ^ ^ |
> + | | | | |
> + | +---------+ +---------+ +---------+ |
> + | | PCH-LPC | | Devices | | Devices | |
> + | +---------+ +---------+ +---------+ |
> + | ^ |
> + | | |
> + | +---------+ |
> + | | Devices | |
> + | +---------+ |
> + | |
> + | |
> + +---------------------------------------------+
> +
> +Extended IRQ model
> +==================
> +
> +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
> +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
> +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
> +to CPUINTC directly.
> +
> + +--------------------------------------------------------+
> + |:: |
> + | |
> + | +-----+ +---------+ +-------+ |
> + | | IPI | --> | CPUINTC | <-- | Timer | |
> + | +-----+ +---------+ +-------+ |
> + | ^ ^ |
> + | | | |
> + | +---------+ +---------+ +-------+ |
> + | | EIOINTC | | LIOINTC | <-- | UARTs | |
> + | +---------+ +---------+ +-------+ |
> + | ^ ^ |
> + | | | |
> + | +---------+ +---------+ |
> + | | PCH-PIC | | PCH-MSI | |
> + | +---------+ +---------+ |
> + | ^ ^ ^ |
> + | | | | |
> + | +---------+ +---------+ +---------+ |
> + | | PCH-LPC | | Devices | | Devices | |
> + | +---------+ +---------+ +---------+ |
> + | ^ |
> + | | |
> + | +---------+ |
> + | | Devices | |
> + | +---------+ |
> + | |
> + | |
> + +--------------------------------------------------------+
> +
I think for consistency with other diagrams in Documentation/, just use
literal code block, like:
diff --git a/Documentation/loongarch/irq-chip-model.rst b/Documentation/loongarch/irq-chip-model.rst
index 35c962991283ff..3cfd528021de05 100644
--- a/Documentation/loongarch/irq-chip-model.rst
+++ b/Documentation/loongarch/irq-chip-model.rst
@@ -24,40 +24,38 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
to LIOINTC, and then CPUINTC.
- +---------------------------------------------+
- |:: |
- | |
- | +-----+ +---------+ +-------+ |
- | | IPI | --> | CPUINTC | <-- | Timer | |
- | +-----+ +---------+ +-------+ |
- | ^ |
- | | |
- | +---------+ +-------+ |
- | | LIOINTC | <-- | UARTs | |
- | +---------+ +-------+ |
- | ^ |
- | | |
- | +-----------+ |
- | | HTVECINTC | |
- | +-----------+ |
- | ^ ^ |
- | | | |
- | +---------+ +---------+ |
- | | PCH-PIC | | PCH-MSI | |
- | +---------+ +---------+ |
- | ^ ^ ^ |
- | | | | |
- | +---------+ +---------+ +---------+ |
- | | PCH-LPC | | Devices | | Devices | |
- | +---------+ +---------+ +---------+ |
- | ^ |
- | | |
- | +---------+ |
- | | Devices | |
- | +---------+ |
- | |
- | |
- +---------------------------------------------+
+ ::
+
+ +-----+ +---------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +---------+ +-------+
+ ^
+ |
+ +---------+ +-------+
+ | LIOINTC | <-- | UARTs |
+ +---------+ +-------+
+ ^
+ |
+ +-----------+
+ | HTVECINTC |
+ +-----------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | PCH-PIC | | PCH-MSI |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | PCH-LPC | | Devices | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+
Extended IRQ model
==================
@@ -67,35 +65,33 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
to CPUINTC directly.
- +--------------------------------------------------------+
- |:: |
- | |
- | +-----+ +---------+ +-------+ |
- | | IPI | --> | CPUINTC | <-- | Timer | |
- | +-----+ +---------+ +-------+ |
- | ^ ^ |
- | | | |
- | +---------+ +---------+ +-------+ |
- | | EIOINTC | | LIOINTC | <-- | UARTs | |
- | +---------+ +---------+ +-------+ |
- | ^ ^ |
- | | | |
- | +---------+ +---------+ |
- | | PCH-PIC | | PCH-MSI | |
- | +---------+ +---------+ |
- | ^ ^ ^ |
- | | | | |
- | +---------+ +---------+ +---------+ |
- | | PCH-LPC | | Devices | | Devices | |
- | +---------+ +---------+ +---------+ |
- | ^ |
- | | |
- | +---------+ |
- | | Devices | |
- | +---------+ |
- | |
- | |
- +--------------------------------------------------------+
+ ::
+
+ +-----+ +---------+ +-------+
+ | IPI | --> | CPUINTC | <-- | Timer |
+ +-----+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+ +-------+
+ | EIOINTC | | LIOINTC | <-- | UARTs |
+ +---------+ +---------+ +-------+
+ ^ ^
+ | |
+ +---------+ +---------+
+ | PCH-PIC | | PCH-MSI |
+ +---------+ +---------+
+ ^ ^ ^
+ | | |
+ +---------+ +---------+ +---------+
+ | PCH-LPC | | Devices | | Devices |
+ +---------+ +---------+ +---------+
+ ^
+ |
+ +---------+
+ | Devices |
+ +---------+
+
+
ACPI-related definitions
========================
Otherwise, htmldocs builds successfully without any new warnings related
to this patch series.
Tested-by: Bagas Sanjaya <bagasdotme@gmail.com>
--
An old man doll... just what I always wanted! - Clara
next prev parent reply other threads:[~2022-06-03 1:45 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-02 11:51 [PATCH V14 00/24] arch: Add basic LoongArch support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 01/24] irqchip: Adjust Kconfig for Loongson Huacai Chen
2022-06-02 13:25 ` Marc Zyngier
2022-06-02 16:34 ` Randy Dunlap
2022-06-03 5:04 ` Huacai Chen
2022-06-02 11:51 ` [PATCH V14 02/24] irqchip/loongson-liointc: Fix build error for LoongArch Huacai Chen
2022-06-02 13:24 ` Marc Zyngier
2022-06-02 11:51 ` [PATCH V14 03/24] Documentation: LoongArch: Add basic documentations Huacai Chen
2022-06-03 1:45 ` Bagas Sanjaya [this message]
2022-06-03 5:27 ` Huacai Chen
2022-06-03 7:35 ` Bagas Sanjaya
2022-06-03 13:01 ` Huacai Chen
2022-06-02 11:51 ` [PATCH V14 04/24] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen
2022-06-02 11:51 ` [PATCH V14 05/24] LoongArch: Add ELF-related definitions Huacai Chen
2022-06-02 11:51 ` [PATCH V14 06/24] LoongArch: Add writecombine support for drm Huacai Chen
2022-06-02 11:51 ` [PATCH V14 07/24] LoongArch: Add build infrastructure Huacai Chen
2022-06-02 11:51 ` [PATCH V14 08/24] LoongArch: Add CPU definition headers Huacai Chen
2022-06-02 11:51 ` [PATCH V14 09/24] LoongArch: Add atomic/locking headers Huacai Chen
2022-06-02 11:51 ` [PATCH V14 10/24] LoongArch: Add other common headers Huacai Chen
2022-06-02 11:51 ` [PATCH V14 11/24] LoongArch: Add boot and setup routines Huacai Chen
2022-06-02 14:09 ` Steps forward for the LoongArch UEFI bringup patch? (was: Re: [PATCH V14 11/24] LoongArch: Add boot and setup routines) WANG Xuerui
2022-06-02 16:14 ` Ard Biesheuvel
2022-06-02 16:29 ` Arnd Bergmann
2022-06-03 5:13 ` Huacai Chen
2022-06-03 9:32 ` Xi Ruoyao
2022-06-03 9:48 ` WANG Xuerui
2022-06-03 10:08 ` Arnd Bergmann
2022-06-02 11:51 ` [PATCH V14 12/24] LoongArch: Add exception/interrupt handling Huacai Chen
2022-06-02 11:51 ` [PATCH V14 13/24] LoongArch: Add process management Huacai Chen
2022-06-02 11:51 ` [PATCH V14 14/24] LoongArch: Add memory management Huacai Chen
2022-06-02 11:51 ` [PATCH V14 15/24] LoongArch: Add system call support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 16/24] LoongArch: Add signal handling support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 17/24] LoongArch: Add ELF and module support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 18/24] LoongArch: Add misc common routines Huacai Chen
2022-06-02 11:51 ` [PATCH V14 19/24] LoongArch: Add some library functions Huacai Chen
2022-06-02 11:51 ` [PATCH V14 20/24] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 21/24] LoongArch: Add multi-processor (SMP) support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 22/24] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2022-06-02 11:51 ` [PATCH V14 23/24] LoongArch: Add Loongson-3 default config file Huacai Chen
2022-06-02 11:51 ` [PATCH V14 24/24] MAINTAINERS: Add maintainer information for LoongArch Huacai Chen
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