From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4934ACCA47A for ; Tue, 14 Jun 2022 08:03:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355587AbiFNIDZ (ORCPT ); Tue, 14 Jun 2022 04:03:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231437AbiFNIDX (ORCPT ); Tue, 14 Jun 2022 04:03:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0819E2CDE9 for ; Tue, 14 Jun 2022 01:03:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 69959613EA for ; Tue, 14 Jun 2022 08:03:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7729EC3411B; Tue, 14 Jun 2022 08:03:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1655193801; bh=xNEEaInH/LKZoWtvuDlNJaZfqiWphsqqnVIIBffqYSU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=CIFjPhFu8bPc91HKOrRVeGWc64yPgQgu7Nx798L2QcZin1rlE/8KfDHbDsw0J3lH+ 0ATgSyb5u3AMCxOU4RiaOqTLFgl7m5b7hotaQlJ4f7v/lyeVKhUvFyHgPGT3UYsRrZ EmmHQbOvTL/oHlyjWzm/BWTw/IO/GrC//gTtJYDQ= Date: Tue, 14 Jun 2022 10:03:18 +0200 From: Greg KH To: Wenhu Wang Cc: Christophe Leroy , "mpe@ellerman.id.au" , "linuxppc-dev@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 2/2] uio:powerpc:mpc85xx: l2-cache-sram uio driver implementation Message-ID: References: <20220609102855.272270-1-wenhu.wang@hotmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 14, 2022 at 07:53:46AM +0000, Wenhu Wang wrote: > >> >> + > >> >> +struct mpc85xx_l2ctlr { > >> >> + u32 ctl; /* 0x000 - L2 control */ > >> > > >> >What is the endian of these u32 values? You map them directly to > >> >memory, so they must be specified some way, right? Please make it > >> >obvious what they are. > >> > > >> > >> Surely, the values should be u32 here, modified in v2 > >> The controller info could be found in > >> "QorIQ¢â P2020 Integrated Processor Reference Manual" > >> "Chapter 6 L2 Look-Aside Cache/SRAM" > >> See: http://m4udit.dinauz.org/P2020RM_rev0.pdf > > > >That's not the answer to my question :) > > > >These are big-endian, right? Please mark them as such and access them > >properly with the correct functions. > > Yes, they are big-edian. > Does it work to add comments(about order and access functions) for the structure ahead of it£¿ > And appending like "_be", "_access_be" or "_big_endian"? (struct mpc85xx_l2ctlr_be {¡¦¡¦}; No, not comments, these should be of the type __be32, right? thanks, greg k-h