From: Huang Rui <ray.huang@amd.com>
To: "Yuan, Perry" <Perry.Yuan@amd.com>
Cc: "rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
"viresh.kumar@linaro.org" <viresh.kumar@linaro.org>,
"Sharma, Deepak" <Deepak.Sharma@amd.com>,
"Limonciello, Mario" <Mario.Limonciello@amd.com>,
"Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
"Huang, Shimmer" <Shimmer.Huang@amd.com>,
"Du, Xiaojian" <Xiaojian.Du@amd.com>,
"Meng, Li (Jassmine)" <Li.Meng@amd.com>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 01/13] x86/msr: Add the MSR definition for AMD CPPC hardware control.
Date: Tue, 19 Jul 2022 08:25:23 +0800 [thread overview]
Message-ID: <YtX586RDd9Xw44IO@amd.com> (raw)
In-Reply-To: <ca830355f1470ce53cd56917b0adee66c0b50f00.1657876961.git.Perry.Yuan@amd.com>
On Fri, Jul 15, 2022 at 06:04:20PM +0800, Yuan, Perry wrote:
> This MSR can be used for controlling whether the CPU boost state
> is enabled in the hardware.
>
> AMD Processor Programming Reference (PPR)
> Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095]
> Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162]
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> arch/x86/include/asm/msr-index.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index d27e0581b777..869508de8269 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -548,6 +548,7 @@
> #define MSR_AMD_CPPC_CAP2 0xc00102b2
> #define MSR_AMD_CPPC_REQ 0xc00102b3
> #define MSR_AMD_CPPC_STATUS 0xc00102b4
> +#define MSR_AMD_CPPC_HW_CTL 0xc0010015
It's actually the duplicated macro definition with MSR_K7_HWCR:
#define MSR_K7_HWCR 0xc0010015
Thanks,
Ray
>
> #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
> #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
> --
> 2.32.0
>
next prev parent reply other threads:[~2022-07-19 0:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 10:03 [PATCH v4 00/13] AMD Pstate Enhancement And Issue Fixs Perry Yuan
2022-07-15 10:04 ` [PATCH v4 01/13] x86/msr: Add the MSR definition for AMD CPPC hardware control Perry Yuan
2022-07-19 0:25 ` Huang Rui [this message]
2022-07-15 10:04 ` [PATCH v4 02/13] cpufreq: amd-pstate: enable AMD Precision Boost mode switch Perry Yuan
2022-07-19 0:45 ` Huang Rui
2022-07-21 9:15 ` Yuan, Perry
2022-07-15 10:04 ` [PATCH v4 03/13] cpufreq: amd-pstate: cleanup the unused and duplicated headers declaration Perry Yuan
2022-07-19 0:46 ` Huang Rui
2022-07-15 10:04 ` [PATCH v4 04/13] cpufreq: amd-pstate: prefetch cppc_req_cached value in amd_pstate_cpu_init() Perry Yuan
2022-07-19 0:48 ` Huang Rui
2022-07-15 10:04 ` [PATCH v4 05/13] cpufreq: amd-pstate: simplify cpudata pointer assignment Perry Yuan
2022-07-19 0:49 ` Huang Rui
2022-07-15 10:04 ` [PATCH v4 06/13] cpufreq: amd_pstate: fix wrong lowest perf fetch Perry Yuan
2022-07-19 0:50 ` Huang Rui
2022-07-15 10:04 ` [PATCH v4 07/13] cpufreq: amd_pstate: map desired perf into pstate scope for powersave governor Perry Yuan
2022-07-19 0:56 ` Huang Rui
2022-07-15 10:04 ` [PATCH v4 08/13] cpufreq: amd-pstate: fix white-space Perry Yuan
2022-07-19 0:58 ` Huang Rui
2022-07-15 10:04 ` [PATCH v4 09/13] cpufreq: amd-pstate: update pstate frequency transition delay time Perry Yuan
2022-07-15 10:04 ` [PATCH v4 10/13] cpufreq: amd-pstate: add ACPI disabled check in acpi_cpc_valid() Perry Yuan
2022-07-15 10:04 ` [PATCH v4 11/13] cpufreq: amd_pstate: update transition delay time to 1ms Perry Yuan
2022-07-19 1:04 ` Huang Rui
2022-07-19 6:33 ` Yuan, Perry
2022-07-15 10:04 ` [PATCH v4 12/13] arch_topology: remove the acpi_disabled check Perry Yuan
2022-07-15 10:04 ` [PATCH v4 13/13] cpufreq: CPPC: " Perry Yuan
2022-07-19 1:07 ` Huang Rui
2022-07-19 6:32 ` Yuan, Perry
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