From: Peter Zijlstra <peterz@infradead.org>
To: Hector Martin <marcan@marcan.st>
Cc: Boqun Feng <boqun.feng@gmail.com>, Will Deacon <will@kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Greg KH <gregkh@linuxfoundation.org>,
jirislaby@kernel.org, Marc Zyngier <maz@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Asahi Linux <asahi@lists.linux.dev>,
Oliver Neukum <oneukum@suse.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: Debugging a TTY race condition on M1 (memory ordering dragons)
Date: Mon, 15 Aug 2022 21:38:41 +0200 [thread overview]
Message-ID: <YvqgwVzlM9vfb8Ko@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <f3f84fc1-50be-0a9b-0538-6ea26dd93b16@marcan.st>
On Tue, Aug 16, 2022 at 04:15:00AM +0900, Hector Martin wrote:
> FWIW, I didn't actually use a full barrier in my patch. I just replaced
> the test_and_set_bit() with the underlying atomic op, sans early exit path.
That isn't quite true; you used atomic_long_fetch_or() which is used in
the generic implementation, but x86 would end up using "LOCK BTS" for
arch_test_and_set_bit(), while atomic_*fetch_or() ends up being a "LOCK
CMPXCHG" loop (which is significantly worse, performance wise).
That said; I don't have a nice solution that works well across the
various architectures.
(in one previous instance of this problem we ended up using a
cmpxchg_relaxed() coupled with an smp_mb__before_atomic(), but there is
no relaxed version of test_and_set_bit())
prev parent reply other threads:[~2022-08-15 22:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 11:16 Debugging a TTY race condition on M1 (memory ordering dragons) Hector Martin
2022-08-15 13:47 ` Will Deacon
2022-08-15 13:56 ` Peter Zijlstra
2022-08-15 16:01 ` Hector Martin
2022-08-15 18:04 ` Boqun Feng
2022-08-15 18:26 ` Hector Martin
2022-08-15 18:58 ` Boqun Feng
2022-08-15 19:15 ` Hector Martin
2022-08-15 19:24 ` Boqun Feng
2022-08-15 19:38 ` Peter Zijlstra [this message]
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