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Date:   Tue, 30 Aug 2022 10:43:38 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Roger Quadros <rogerq@kernel.org>
Cc:     kishon@ti.com, vigneshr@ti.com, t-patil@ti.com,
        sjakhade@cadence.com, s-vadapalli@ti.com,
        linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org
Subject: Re: [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g
Message-ID: <Yw2cgthIiLONb/+Y@matsya>
References: <20220628122255.24265-1-rogerq@kernel.org>
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On 28-06-22, 15:22, Roger Quadros wrote:
> Hi,
> 
> The SERDES in J7200 SR2.0 supports 2 reference clocks.
> The second reference clock (core_ref1_clk) is hardwired to
> MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).
> 
> Add a new compatible "j7200-wiz-10g" for this device.
> 
> The external clocks to SERDES PLL refclock mapping is now
> controlled by a special register in System Control Module
> (SCM) space. Add a property "ti,scm" to reference it and
> configure it in the driver.

Applied, thanks

-- 
~Vinod