From: Andrew Lunn <andrew@lunn.ch>
To: Jagan Teki <jagan@edgeble.ai>
Cc: Anand Moon <anand@edgeble.ai>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Jose Abreu <joabreu@synopsys.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Sugar Zhang <sugar.zhang@rock-chips.com>,
David Wu <david.wu@rock-chips.com>,
netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126 support
Date: Thu, 1 Sep 2022 14:12:36 +0200 [thread overview]
Message-ID: <YxChtBzavS1Fooxs@lunn.ch> (raw)
In-Reply-To: <CA+VMnFzNcPesS8Mn2mwr-RDXf5sRz-2A3K+syDmpCo1va6JwMw@mail.gmail.com>
On Thu, Sep 01, 2022 at 12:56:09PM +0530, Jagan Teki wrote:
> On Mon, 29 Aug 2022 at 18:40, Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > On Mon, Aug 29, 2022 at 06:50:42AM +0000, Anand Moon wrote:
> > > Rockchip RV1126 has GMAC 10/100/1000M ethernet controller
> > > via RGMII and RMII interfaces are configured via M0 and M1 pinmux.
> > >
> > > This patch adds rv1126 support by adding delay lines of M0 and M1
> > > simultaneously.
> >
> > What does 'delay lines' mean with respect to RGMII?
>
> These are MAC receive clock delay lengths.
>
> >
> > The RGMII signals need a 2ns delay between the clock and the data
> > lines. There are three places this can happen:
> >
> > 1) In the PHY
> > 2) Extra long lines on the PCB
> > 3) In the MAC
> >
> > Generally, 1) is used, and controlled via phy-mode. A value of
> > PHY_INTERFACE_MODE_RGMII_ID passed to the PHY driver means it will add
> > these delays.
> >
> > You don't want both the MAC and the PHY adding delays.
>
> Yes, but these are specific to MAC, not related to PHY delays. Similar
> to what is there in other Rockchip SoC families like RK3366, 3368,
> 3399, 3128, but these MAC clock delay lengths are grouped based on the
> iomux group in RV1126. We have iomux group 0 (M0) and group 1 (M1), so
> the rgmii has to set these lengths irrespective of whether PHY add's
> or not.
So this is just fine tuning, in the order of pico seconds?
If that is all it is, then this is fine. It becomes a problem when it
is 2ns.
Andrew
next prev parent reply other threads:[~2022-09-01 12:13 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-29 6:50 [PATCH 1/2] dt-bindings: net: rockchip-dwmac: add rv1126 compatible string Anand Moon
2022-08-29 6:50 ` [PATCH 2/2] net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126 support Anand Moon
2022-08-29 13:09 ` Andrew Lunn
2022-09-01 7:06 ` Anand Moon
2022-09-01 12:08 ` Andrew Lunn
2022-09-01 7:26 ` Jagan Teki
2022-09-01 12:12 ` Andrew Lunn [this message]
2022-09-02 8:51 ` Jagan Teki
2022-08-29 10:20 ` [PATCH 1/2] dt-bindings: net: rockchip-dwmac: add rv1126 compatible string Heiko Stübner
2022-08-30 9:51 ` Krzysztof Kozlowski
2022-09-01 7:06 ` Anand Moon
2022-08-30 10:00 ` Jagan Teki
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