From: Sean Christopherson <seanjc@google.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 05/12] KVM: x86/pmu: Error when user sets the GLOBAL_STATUS reserved bits
Date: Thu, 6 Apr 2023 16:45:46 -0700 [thread overview]
Message-ID: <ZC9Zqn/+J5vaXKfo@google.com> (raw)
In-Reply-To: <20230214050757.9623-6-likexu@tencent.com>
On Tue, Feb 14, 2023, Like Xu wrote:
> From: Like Xu <likexu@tencent.com>
>
> If the user space sets reserved bits when restoring the MSR_CORE_
> PERF_GLOBAL_STATUS register, these bits will be accidentally returned
> when the guest runs a read access to this register, and cannot be cleared
> up inside the guest, which makes the guest's PMI handler very confused.
The changelog needs to state what the patch actually does.
> Signed-off-by: Like Xu <likexu@tencent.com>
> ---
> arch/x86/kvm/vmx/pmu_intel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 904f832fc55d..aaea25d2cae8 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -397,7 +397,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> reprogram_fixed_counters(pmu, data);
> break;
> case MSR_CORE_PERF_GLOBAL_STATUS:
> - if (!msr_info->host_initiated)
> + if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask))
This is wrong. Bits 60:58 are reserved in IA32_PERF_GLOBAL_OVF_CTRL, but are
ASCI, CTR_FREEZE, and LBR_FREEZE respectively in MSR_CORE_PERF_GLOBAL_STATUS.
> return 1; /* RO MSR */
>
> pmu->global_status = data;
> --
> 2.39.1
>
next prev parent reply other threads:[~2023-04-06 23:46 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 5:07 [PATCH v4 00/12] KVM: x86: Add AMD Guest PerfMonV2 PMU support Like Xu
2023-02-14 5:07 ` [PATCH v4 01/12] KVM: x86/pmu: Rename pmc_is_enabled() to pmc_is_globally_enabled() Like Xu
2023-02-14 5:07 ` [PATCH v4 02/12] KVM: VMX: Refactor intel_pmu_set_msr() to align with other set_msr() helpers Like Xu
2023-02-16 21:13 ` Sean Christopherson
2023-02-21 8:44 ` Like Xu
2023-03-23 7:43 ` Like Xu
2023-03-23 14:28 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 03/12] KVM: x86/pmu: Rewrite reprogram_counters() to improve performance Like Xu
2023-02-14 5:07 ` [PATCH v4 04/12] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Like Xu
2023-02-14 5:07 ` [PATCH v4 05/12] KVM: x86/pmu: Error when user sets the GLOBAL_STATUS reserved bits Like Xu
2023-04-06 23:45 ` Sean Christopherson [this message]
2023-04-07 5:08 ` Like Xu
2023-04-07 15:43 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 06/12] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Like Xu
2023-04-06 23:57 ` Sean Christopherson
2023-04-07 1:39 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 07/12] KVM: x86/cpuid: Use fast return for cpuid "0xa" leaf when !enable_pmu Like Xu
2023-04-06 23:59 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 08/12] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Like Xu
2023-04-07 0:06 ` Sean Christopherson
2023-04-07 0:23 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 09/12] KVM: x86/pmu: Forget PERFCTR_CORE if the min " Like Xu
2023-04-07 0:32 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 10/12] KVM: x86/cpuid: Add X86_FEATURE_PERFMON_V2 as a scattered flag Like Xu
2023-04-07 0:41 ` Sean Christopherson
2023-02-14 5:07 ` [PATCH v4 11/12] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Like Xu
2023-04-07 1:35 ` Sean Christopherson
2023-04-07 7:08 ` Like Xu
2023-04-07 14:44 ` Sean Christopherson
2023-04-10 11:34 ` Like Xu
2023-02-14 5:07 ` [PATCH v4 12/12] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 Like Xu
2023-04-07 1:50 ` Sean Christopherson
2023-04-07 7:19 ` Like Xu
2023-04-07 2:02 ` [PATCH v4 00/12] KVM: x86: Add AMD Guest PerfMonV2 PMU support Sean Christopherson
2023-04-07 7:28 ` Like Xu
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