From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BEFAEB64DC for ; Mon, 10 Jul 2023 20:24:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229577AbjGJUY3 (ORCPT ); Mon, 10 Jul 2023 16:24:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230465AbjGJUYX (ORCPT ); Mon, 10 Jul 2023 16:24:23 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B4CB198; Mon, 10 Jul 2023 13:24:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=G0ut9Msx8avXgkOpqAa+A7Dar6d8OWfnht1FICkF8CU=; b=FOqO3cdm12VAe6nUmn7GX8ljm1 IVWHYgztJseuOAdpb0Kl7UTesY1zGNKYMs5e5EBFqrZ0ooTqGXwH4QeLUQbdv8JXL7fENKqEe6VjM SQXo/iyUUboIV1vXsJOTyGvNvvsYwJ5gWy8hUjxBQylojeQqUVVDk4Ovc3cmoCOmdphg5mAVEP7Uf kRZ+dXmJA1uRht41tVmc5AzHGP5F+rFYYcIAo7BH8Z6T/u7Q9ThfhPZILyYI1SpBKAx3x4ScvmVJX IrVLMuAKMIcKwmG/6tZECnJSU/lD3HpvUDf7IhlthMI3jSUs6ymuZ6XM25REdQ3J2tYwnjueQOVet T7JE38Vg==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1qIxQd-00Etrn-OE; Mon, 10 Jul 2023 20:24:15 +0000 Date: Mon, 10 Jul 2023 21:24:15 +0100 From: Matthew Wilcox To: Christophe Leroy Cc: "linux-arch@vger.kernel.org" , "linux-mm@kvack.org" , "linux-kernel@vger.kernel.org" , Michael Ellerman , Nicholas Piggin , "linuxppc-dev@lists.ozlabs.org" Subject: Re: [PATCH v4 20/36] powerpc: Implement the new page table range API Message-ID: References: <20230315051444.3229621-1-willy@infradead.org> <20230315051444.3229621-21-willy@infradead.org> <1743d96f-8efe-0127-2cae-7368ce0eb2e6@csgroup.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Mar 18, 2023 at 09:19:04AM +0000, Christophe Leroy wrote: > void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep, > pte_t pte, unsigned int nr) > { > pgprot_t prot; > unsigned long pfn; > /* > * Make sure hardware valid bit is not set. We don't do > * tlb flush for this update. > */ > VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); > > /* Note: mm->context.id might not yet have been assigned as > * this context might not have been activated yet when this > * is called. > */ > pte = set_pte_filter(pte); > > prot = pte_pgprot(pte); > pfn = pte_pfn(pte); > /* Perform the setting of the PTE */ > for (;;) { > __set_pte_at(mm, addr, ptep, pfn_pte(pfn, prot), 0); > if (--nr == 0) > break; > ptep++; > pfn++; > addr += PAGE_SIZE; > } > } I'd rather the per-arch code were as similar to each other and the generic implementation as possible. Fewer bugs that way and easier for other people to make changes that have to touch every architecture in the future.