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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A15CEFEC; Mon, 19 Feb 2024 07:35:57 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.64.104]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7E8103F762; Mon, 19 Feb 2024 07:35:16 -0800 (PST) Date: Mon, 19 Feb 2024 15:35:08 +0000 From: Mark Rutland To: Marc Zyngier Cc: Catalin Marinas , Stephen Rothwell , Christoffer Dall , Will Deacon , Ard Biesheuvel , Linux Kernel Mailing List , Linux Next Mailing List , Oliver Upton Subject: Re: linux-next: manual merge of the kvm-arm tree with the arm64 tree Message-ID: References: <20240219135805.1c4138a3@canb.auug.org.au> <86bk8c4gyh.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86bk8c4gyh.wl-maz@kernel.org> On Mon, Feb 19, 2024 at 03:22:14PM +0000, Marc Zyngier wrote: > From f24638a5f41424faf47f3d9035e6dcbd3800fcb6 Mon Sep 17 00:00:00 2001 > From: Marc Zyngier > Date: Mon, 19 Feb 2024 15:13:22 +0000 > Subject: [PATCH] arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and > VARange > > Open-coding the feature matching parameters for LVA/LVA2 leads to > issues with upcoming changes to the cpufeature code. > > By making TGRAN{4,16,64} and VARange signed/unsigned as per the > architecture, we can use the existing macros, making the feature > match robust against those changes. > > Signed-off-by: Marc Zyngier I think this is the right thing to do; the patch itself looks good to me, so FWIW: Acked-by: Mark Rutland Mark. > --- > arch/arm64/kernel/cpufeature.c | 15 +++------------ > arch/arm64/tools/sysreg | 8 ++++---- > 2 files changed, 7 insertions(+), 16 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 8f9665e8774b..2119e9dd0c4e 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2791,24 +2791,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .capability = ARM64_HAS_VA52, > .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, > .matches = has_cpuid_feature, > - .field_width = 4, > #ifdef CONFIG_ARM64_64K_PAGES > .desc = "52-bit Virtual Addressing (LVA)", > - .sign = FTR_SIGNED, > - .sys_reg = SYS_ID_AA64MMFR2_EL1, > - .field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT, > - .min_field_value = ID_AA64MMFR2_EL1_VARange_52, > + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) > #else > .desc = "52-bit Virtual Addressing (LPA2)", > - .sys_reg = SYS_ID_AA64MMFR0_EL1, > #ifdef CONFIG_ARM64_4K_PAGES > - .sign = FTR_SIGNED, > - .field_pos = ID_AA64MMFR0_EL1_TGRAN4_SHIFT, > - .min_field_value = ID_AA64MMFR0_EL1_TGRAN4_52_BIT, > + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) > #else > - .sign = FTR_UNSIGNED, > - .field_pos = ID_AA64MMFR0_EL1_TGRAN16_SHIFT, > - .min_field_value = ID_AA64MMFR0_EL1_TGRAN16_52_BIT, > + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) > #endif > #endif > }, > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index fa3fe0856880..670a33fca3bc 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1540,16 +1540,16 @@ Enum 35:32 TGRAN16_2 > 0b0010 IMP > 0b0011 52_BIT > EndEnum > -Enum 31:28 TGRAN4 > +SignedEnum 31:28 TGRAN4 > 0b0000 IMP > 0b0001 52_BIT > 0b1111 NI > EndEnum > -Enum 27:24 TGRAN64 > +SignedEnum 27:24 TGRAN64 > 0b0000 IMP > 0b1111 NI > EndEnum > -Enum 23:20 TGRAN16 > +UnsignedEnum 23:20 TGRAN16 > 0b0000 NI > 0b0001 IMP > 0b0010 52_BIT > @@ -1697,7 +1697,7 @@ Enum 23:20 CCIDX > 0b0000 32 > 0b0001 64 > EndEnum > -Enum 19:16 VARange > +UnsignedEnum 19:16 VARange > 0b0000 48 > 0b0001 52 > EndEnum > -- > 2.39.2 > > > -- > Without deviation from the norm, progress is not possible.