From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2442CC433E0 for ; Tue, 12 Jan 2021 12:36:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0A1223110 for ; Tue, 12 Jan 2021 12:36:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387627AbhALMgn (ORCPT ); Tue, 12 Jan 2021 07:36:43 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10652 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726405AbhALMgm (ORCPT ); Tue, 12 Jan 2021 07:36:42 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DFVQW1gZwz15s2n; Tue, 12 Jan 2021 20:34:59 +0800 (CST) Received: from [127.0.0.1] (10.174.176.220) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 20:35:52 +0800 Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller To: Arnd Bergmann CC: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel References: <20210112015602.497-1-thunder.leizhen@huawei.com> <20210112015602.497-3-thunder.leizhen@huawei.com> From: "Leizhen (ThunderTown)" Message-ID: Date: Tue, 12 Jan 2021 20:35:50 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/1/12 16:46, Arnd Bergmann wrote: > On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei wrote: > >> +--- >> +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Hisilicon L3 cache controller >> + >> +maintainers: >> + - Wei Xu >> + >> +description: | >> + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical >> + addresses. The data cached in the L3 outer cache can be operated based on the >> + physical address range or the entire cache. >> + >> +properties: >> + compatible: >> + items: >> + - const: hisilicon,l3cache >> + > > The compatible string needs to be a little more specific, I'm sure > you cannot guarantee that this is the only L3 cache controller ever > designed in the past or future by HiSilicon. > > Normally when you have an IP block that is itself unnamed but that is specific > to one or a few SoCs but that has no na, the convention is to include the name > of the first SoC that contained it. Right, thanks for your suggestion, I will rename it to "hisilicon,hi1381-l3cache" and "hisilicon,hi1215-l3cache". > > Can you share which products actually use this L3 cache controller? This L3 cache controller is used on Hi1381 and Hi1215 board. I don't know where these two boards are used. Our company is too large. Software is delivered level by level. I'm only involved in the Kernel-related part. > > On a related note, what does the memory map look like on this chip? memory@a00000 { device_type = "memory"; reg = <0x0 0xa00000 0x0 0x1aa00000>, <0x1 0xe0000000 0x0 0x1d000000>, <0x0 0x1f400000 0x0 0xb5c00000>; }; Currently, the DTS is being maintained by ourselves, I'll try to upstream it later. > Do you support more than 4GB of total installed memory? If you Currently, the total size does not exceed 4 GB. However, the physical address is wider than 32 bits. > do, this becomes a problem in the future as highmem support > winds down. In fact anything more than 1GB on a 32-bit system > requires more work on the kernel to be completed before we remove > highmem, and will incur a slowdown. If the total is under 4GB but the > memory is not in a contiguous physical address range. See my > Linaro connect presentation[1] for further information on the topic. Great. > > Arnd > > [1] https://connect.linaro.org/resources/lvc20/lvc20-106/ > > . >