From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0AFFC4708B for ; Thu, 27 May 2021 13:16:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8769461073 for ; Thu, 27 May 2021 13:16:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236395AbhE0NS2 (ORCPT ); Thu, 27 May 2021 09:18:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236369AbhE0NSY (ORCPT ); Thu, 27 May 2021 09:18:24 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C614C061760; Thu, 27 May 2021 06:16:50 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id j10so792438edw.8; Thu, 27 May 2021 06:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bJxa6D61sNyoVcUGq0JgZ9RhtqSvpqxNVEv5UpFQHpA=; b=e1jtJrfvCnON7Zgry3taHlpF2S7Ok7Wps42CM9sF8A1X+sidOqveg1wBeTO/2446u0 AvKeUwT1HI336OPftLTxktnKtqpMZfAv4N8UYTf8xbhq4x7uaaK9vOuARa4I+YMok4we kOYEs8JbbO0qg/7u36OEVq+28T++BBWN038cm9W3/PHlz92yg4dEb3s9gEAu1rjNMLbu X7E9E3xtEPqD3WED5Kh2KqykNKGpRDkaLBj8/0rU4/OXC+SgBcvu8lAAKVdiUQyLHVAk ERWQDkYNNSQOqzRv+nj96mYrVGn7es9ssW3qsOHk3wz4fqLn8Iv3qixF6pklYMkQ+dBn HWZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bJxa6D61sNyoVcUGq0JgZ9RhtqSvpqxNVEv5UpFQHpA=; b=D4ok19iNKIEreYmESYKfqeK+TnbnDDMwwLbd2q9PYZuBsPB368f/qwS2IHUnCMQKKs pHa0Lc5zdKqICG3Gtuz/s/8HV2FRiXXWPOZSSJd3PMGAcwg/u6M4LQvFs2reUuAANd3Y DeUSaQj9FRBegBwqqbai+OzlcdjydTLtQybJJqJHR/6HIkRj0VcC5aSOhujKdAiaIxP2 BA75TEIiiPBYVGgoA1OiIKNi37bsHFYQEYmGiAvMX0peAj0XhQq4e4/WNlU4Km9UU0w6 FNUghMa8V1ZOOfnda2At1SiV9YPKW4T9GM3Hjv8B/XMOJhs5aOfjP15k3OsK7cm7YFF7 pS5A== X-Gm-Message-State: AOAM533KuWJx+YDuHl/HFjmhBQzIVXfDyMPcE9S0yHFMdY1/VFKcP5xh avuu5/JU5jWBwhmwF9mLsSJlc3c+Bjg= X-Google-Smtp-Source: ABdhPJzFuBN1+LhAPjeaQrdY/nYNobVtmWAtIzt6XqXwol07HBpqkSFkn/XCqv/slWM0wKn5n9PNPg== X-Received: by 2002:a50:ff16:: with SMTP id a22mr4037741edu.143.1622121408643; Thu, 27 May 2021 06:16:48 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:48 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC Date: Thu, 27 May 2021 16:16:39 +0300 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v2: - Added Reviewed-by from Mani drivers/clk/actions/owl-s500.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 61bb224f6330..75b7186185b0 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -305,7 +305,7 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, @@ -317,31 +317,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, -- 2.31.1