From: WANG Xuerui <kernel@xen0n.name>
To: Jianmin Lv <lvjianmin@loongson.cn>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>
Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>,
loongson-kernel@lists.loongnix.cn,
Liu Peibao <liupeibao@loongson.cn>,
stable@vger.kernel.org
Subject: Re: [PATCH V1 2/4] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment
Date: Sun, 21 May 2023 18:31:04 +0800 [thread overview]
Message-ID: <a31415d5-ca4e-49fa-60d7-9cd53ba5a680@xen0n.name> (raw)
In-Reply-To: <20230520063818.27208-3-lvjianmin@loongson.cn>
On 2023/5/20 14:38, Jianmin Lv wrote:
> From: Liu Peibao <liupeibao@loongson.cn>
>
> In DeviceTree path, when ht_vec_base is not zero, the hwirq of PCH PIC will
> be assigned incorrectly. Because when pch_pic_domain_translate() adds the
> ht_vec_base to hwirq, the hwirq dose not subtract the ht_vec_base when
"does not have the ht_vec_base subtracted"?
> calling irq_domain_set_info().
>
> The ht_vec_base is designed for the parent irq chip/domain of the PCH PIC.
> It seems not proper to deal this in callbacks of the PCH PIC domain and
> let's put this back like the initial commit ef8c01eb64ca ("irqchip: Add
> Loongson PCH PIC controller").
>
> Fixes: bcdd75c596c8 ("irqchip/loongson-pch-pic: Add ACPI init support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Liu Peibao <liupeibao@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> ---
> drivers/irqchip/irq-loongson-pch-pic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
> index 921c5c0190d1..93a71f66efeb 100644
> --- a/drivers/irqchip/irq-loongson-pch-pic.c
> +++ b/drivers/irqchip/irq-loongson-pch-pic.c
> @@ -164,7 +164,7 @@ static int pch_pic_domain_translate(struct irq_domain *d,
> if (fwspec->param_count < 2)
> return -EINVAL;
>
> - *hwirq = fwspec->param[0] + priv->ht_vec_base;
> + *hwirq = fwspec->param[0];
> *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
> } else {
> if (fwspec->param_count < 1)
> @@ -196,7 +196,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
>
> parent_fwspec.fwnode = domain->parent->fwnode;
> parent_fwspec.param_count = 1;
> - parent_fwspec.param[0] = hwirq;
> + parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
>
> err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
> if (err)
--
WANG "xen0n" Xuerui
Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/
next prev parent reply other threads:[~2023-05-21 11:48 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-20 6:38 [PATCH V1 0/4] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
2023-05-20 6:38 ` [PATCH V1 1/4] irqchip/loongson-pch-pic: Fix initialization of HT vector register Jianmin Lv
2023-05-21 10:29 ` WANG Xuerui
2023-05-22 8:49 ` Jianmin Lv
2023-05-20 6:38 ` [PATCH V1 2/4] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment Jianmin Lv
2023-05-21 10:31 ` WANG Xuerui [this message]
2023-05-22 8:49 ` Jianmin Lv
2023-05-20 6:38 ` [PATCH V1 3/4] irqchip/loongson-liointc: Fix IRQ trigger polarity Jianmin Lv
2023-05-21 10:46 ` WANG Xuerui
2023-05-22 8:58 ` Jianmin Lv
2023-05-20 6:38 ` [PATCH V1 4/4] irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag Jianmin Lv
2023-05-20 8:43 ` Huacai Chen
2023-05-22 9:00 ` Jianmin Lv
2023-06-14 11:14 [PATCH V1 0/4] irqchip/loongson: Fix some loongson irqchip drivers Jianmin Lv
2023-06-14 11:14 ` [PATCH V1 2/4] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment Jianmin Lv
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