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[82.243.161.21]) by smtp.gmail.com with ESMTPSA id e27sm108804445wra.67.2019.01.21.07.36.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Jan 2019 07:36:09 -0800 (PST) Message-ID: Subject: Re: [PATCH 0/3] pinctrl: meson: g12a fixes From: Jerome Brunet To: Linus Walleij , Kevin Hilman Cc: "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:ARM/Amlogic Meson..." , "linux-kernel@vger.kernel.org" Date: Mon, 21 Jan 2019 16:36:08 +0100 In-Reply-To: References: <20190117102315.1833-1-jbrunet@baylibre.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.4 (3.30.4-1.fc29) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2019-01-21 at 14:53 +0100, Linus Walleij wrote: > On Thu, Jan 17, 2019 at 11:23 AM Jerome Brunet wrote: > > > This patchset fixes the initial pinctrl support added for th g12a SoC > > family, which is mainly around the register regions claimed by the > > driver. > > > > Linus, would it possible for you to provide a tag with these changes to > > Kevin ? > > https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-meson-fixes > > > ATM, we can only use the devices for which the pinmux is already set by > > the bootloader. Enabling the broken pinctrl driver could cause regressions > > in kernelCI. Having a tag, would allow us to start using pinctrl on this > > SoC in this cycle, w/o regression. It would be nice :) > > When you say "this cycle" do you mean I should target fixes (v5.0-rcN) > or next (v5.1) with these patches? I was referring to the 5.1 release but it is a good question, I did not really think about 5.0. Those changes are mainly fixes, so guess it could go in the 5.0 but support for this SoC is still in its early stages, so either way is fine by me. Whatever is simpler for you I guess ;) > > Yours, > Linus Walleij