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([2a01:e34:ed2f:f020:70d3:6c26:978:999d]) by smtp.googlemail.com with ESMTPSA id s28sm7343265wra.54.2021.06.04.01.07.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Jun 2021 01:07:10 -0700 (PDT) Subject: Re: [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support To: shruthi.sanil@intel.com, tglx@linutronix.de, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: andriy.shevchenko@linux.intel.com, kris.pan@linux.intel.com, mgross@linux.intel.com, srikanth.thokala@intel.com, lakshmi.bai.raja.subramanian@intel.com, mallikarjunappa.sangannavar@intel.com References: <20210527063906.18592-1-shruthi.sanil@intel.com> <20210527063906.18592-3-shruthi.sanil@intel.com> From: Daniel Lezcano Message-ID: Date: Fri, 4 Jun 2021 10:07:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210527063906.18592-3-shruthi.sanil@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/05/2021 08:39, shruthi.sanil@intel.com wrote: > From: Shruthi Sanil > > The Intel Keem Bay timer driver supports clocksource and clockevent > features for the timer IP used in Intel Keem Bay SoC. > The timer block supports 1 free running counter and 8 timers. > The free running counter can be used as a clocksource and > the timers can be used as clockevent. Each timer is capable of > generating individual interrupt. > Both the features are enabled through the timer general config register. > > Reviewed-by: Andy Shevchenko > Signed-off-by: Shruthi Sanil > --- > MAINTAINERS | 5 + > drivers/clocksource/Kconfig | 11 ++ > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-keembay.c | 255 ++++++++++++++++++++++++++++ > 4 files changed, 272 insertions(+) > create mode 100644 drivers/clocksource/timer-keembay.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 04babfa8fc76..73543ed60e84 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -9278,6 +9278,11 @@ F: drivers/crypto/keembay/keembay-ocs-hcu-core.c > F: drivers/crypto/keembay/ocs-hcu.c > F: drivers/crypto/keembay/ocs-hcu.h > > +INTEL KEEM BAY TIMER SUPPORT > +M: Shruthi Sanil > +S: Maintained > +F: drivers/clocksource/timer-keembay.c > + > INTEL MANAGEMENT ENGINE (mei) > M: Tomas Winkler > L: linux-kernel@vger.kernel.org > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 39aa21d01e05..08f491cf7f61 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -693,4 +693,15 @@ config MICROCHIP_PIT64B > modes and high resolution. It is used as a clocksource > and a clockevent. > > +config KEEMBAY_TIMER > + bool "Intel Keem Bay timer" > + depends on ARCH_KEEMBAY > + select TIMER_OF Please refer to the other timer option to see how we create silent option. We want the Kconfig's platform to select the timer, not the user except for compilation coverage or expert mode. > + help > + This option enables the support for the Intel Keem Bay > + general purpose timer and free running counter driver. > + Each timer can generate an individual interrupt and > + supports oneshot and periodic modes. > + The 64-bit counter can be used as a clock source. > + > endmenu Other than that, LGTM. Thanks -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog