From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FC12C4338F for ; Thu, 12 Aug 2021 09:14:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1F3461058 for ; Thu, 12 Aug 2021 09:14:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235005AbhHLJOi (ORCPT ); Thu, 12 Aug 2021 05:14:38 -0400 Received: from out30-43.freemail.mail.aliyun.com ([115.124.30.43]:53928 "EHLO out30-43.freemail.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232796AbhHLJOg (ORCPT ); Thu, 12 Aug 2021 05:14:36 -0400 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R561e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=e01e04394;MF=xianting.tian@linux.alibaba.com;NM=1;PH=DS;RN=9;SR=0;TI=SMTPD_---0Uim5XHy_1628759649; Received: from B-LB6YLVDL-0141.local(mailfrom:xianting.tian@linux.alibaba.com fp:SMTPD_---0Uim5XHy_1628759649) by smtp.aliyun-inc.com(127.0.0.1); Thu, 12 Aug 2021 17:14:09 +0800 Subject: Re: [PATCH v4 1/2] tty: hvc: pass DMA capable memory to put_chars() To: Arnd Bergmann Cc: gregkh , Jiri Slaby , Amit Shah , Omar Sandoval , linuxppc-dev , "open list:DRM DRIVER FOR QEMU'S CIRRUS DEVICE" , Linux Kernel Mailing List , Guo Ren References: <20210806030138.123479-1-xianting.tian@linux.alibaba.com> <20210806030138.123479-2-xianting.tian@linux.alibaba.com> From: Xianting TIan Message-ID: Date: Thu, 12 Aug 2021 17:14:09 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2021/8/12 下午4:54, Arnd Bergmann 写道: > On Thu, Aug 12, 2021 at 10:08 AM Xianting TIan > wrote: >> 在 2021/8/6 下午10:51, Arnd Bergmann 写道: >>> On Fri, Aug 6, 2021 at 5:01 AM Xianting Tian >>>> +#define __ALIGNED__ __attribute__((__aligned__(sizeof(long)))) >>> I think you need a higher alignment for DMA buffers, instead of sizeof(long), >>> I would suggest ARCH_DMA_MINALIGN. >> As some ARCH(eg, x86, riscv) doesn't define ARCH_DMA_MINALIG, so i think >> it 's better remain the code unchanged, >> >> I will send v5 patch soon. > I think you could just use "L1_CACHE_BYTES" as the alignment in this case. > This will make the structure slightly larger for architectures that do not have > alignment constraints on DMA buffers, but using a smaller alignment is > clearly wrong. Another option would be to use ARCH_KMALLOC_MINALIGN. yes, I unstand you, the align size must  L1_CACHE_BYTES at least. > > Note that there is a patch to add ARCH_DMA_MINALIGN to riscv already, yes, I summited this patch, it is discussing, seems they don't want to apply it. > as some implementations do not have coherent DMA. I had failed to > realized though that on x86 you do not get an ARCH_DMA_MINALIGN > definition. I didn't find the definition in arch/x86/include/asm/cache.h and other place, x86 is dma coherent, it may doesn't need it. > > Arnd