Add Operation State Manager (OSM) L3 provider support on SM8150 and Epoch Subsystem (EPSS) L3 provider support on SM8250 SoCs. Depends on: https://patchwork.kernel.org/cover/11687925/ Sibi Sankar (7): dt-bindings: interconnect: Add OSM L3 DT binding on SM8150 interconnect: qcom: Add OSM L3 support on SM8150 interconnect: qcom: Lay the groundwork for adding EPSS support dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250 interconnect: qcom: Add EPSS L3 support on SM8250 arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider arm64: dts: qcom: sm8250: Add EPSS L3 interconnect provider .../bindings/interconnect/qcom,osm-l3.yaml | 2 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++ drivers/interconnect/qcom/osm-l3.c | 75 ++++++++++++++++--- drivers/interconnect/qcom/sm8150.h | 2 + drivers/interconnect/qcom/sm8250.h | 2 + .../dt-bindings/interconnect/qcom,osm-l3.h | 3 + 7 files changed, 95 insertions(+), 11 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Add Operation State Manager (OSM) L3 interconnect provider binding on SM8150 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 91f70c9067d12..b6945c11eb46b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,sc7180-osm-l3 - qcom,sdm845-osm-l3 + - qcom,sm8150-osm-l3 reg: maxItems: 1 -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Add Operation State Manager (OSM) L3 interconnect provider support on SM8150 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- drivers/interconnect/qcom/osm-l3.c | 15 +++++++++++++++ drivers/interconnect/qcom/sm8150.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 96fb9ff5ff2e8..00831c33e0fe5 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -16,6 +16,7 @@ #include "sc7180.h" #include "sdm845.h" +#include "sm8150.h" #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) @@ -96,6 +97,19 @@ static const struct qcom_icc_desc sc7180_icc_osm_l3 = { .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes), }; +DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3); +DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32); + +static struct qcom_icc_node *sm8150_osm_l3_nodes[] = { + [MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3, + [SLAVE_OSM_L3] = &sm8150_osm_l3, +}; + +static const struct qcom_icc_desc sm8150_icc_osm_l3 = { + .nodes = sm8150_osm_l3_nodes, + .num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes), +}; + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -258,6 +272,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, + { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match); diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h index 3e01ac76ae1db..97996f64d799c 100644 --- a/drivers/interconnect/qcom/sm8150.h +++ b/drivers/interconnect/qcom/sm8150.h @@ -148,5 +148,7 @@ #define SM8150_SLAVE_VSENSE_CTRL_CFG 137 #define SM8150_SNOC_CNOC_MAS 138 #define SM8150_SNOC_CNOC_SLV 139 +#define SM8150_MASTER_OSM_L3_APPS 140 +#define SM8150_SLAVE_OSM_L3 141 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Lay the groundwork for adding Epoch Subsystem (EPSS) L3 support on SM8250. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- drivers/interconnect/qcom/osm-l3.c | 37 +++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 00831c33e0fe5..27c9ece52efda 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -21,13 +21,13 @@ #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) #define LUT_L_VAL GENMASK(7, 0) -#define LUT_ROW_SIZE 32 #define CLK_HW_DIV 2 -/* Register offsets */ +/* OSM Register offsets */ #define REG_ENABLE 0x0 -#define REG_FREQ_LUT 0x110 -#define REG_PERF_STATE 0x920 +#define OSM_LUT_ROW_SIZE 32 +#define OSM_REG_FREQ_LUT 0x110 +#define OSM_REG_PERF_STATE 0x920 #define OSM_L3_MAX_LINKS 1 @@ -37,6 +37,7 @@ struct qcom_osm_l3_icc_provider { void __iomem *base; unsigned int max_state; + unsigned int reg_perf_state; unsigned long lut_tables[LUT_MAX_ENTRIES]; struct icc_provider provider; }; @@ -60,6 +61,9 @@ struct qcom_icc_node { struct qcom_icc_desc { struct qcom_icc_node **nodes; size_t num_nodes; + unsigned int lut_row_size; + unsigned int reg_freq_lut; + unsigned int reg_perf_state; }; #define DEFINE_QNODE(_name, _id, _buswidth, ...) \ @@ -82,6 +86,9 @@ static struct qcom_icc_node *sdm845_osm_l3_nodes[] = { static const struct qcom_icc_desc sdm845_icc_osm_l3 = { .nodes = sdm845_osm_l3_nodes, .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes), + .lut_row_size = OSM_LUT_ROW_SIZE, + .reg_freq_lut = OSM_REG_FREQ_LUT, + .reg_perf_state = OSM_REG_PERF_STATE, }; DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3); @@ -95,6 +102,9 @@ static struct qcom_icc_node *sc7180_osm_l3_nodes[] = { static const struct qcom_icc_desc sc7180_icc_osm_l3 = { .nodes = sc7180_osm_l3_nodes, .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes), + .lut_row_size = OSM_LUT_ROW_SIZE, + .reg_freq_lut = OSM_REG_FREQ_LUT, + .reg_perf_state = OSM_REG_PERF_STATE, }; DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3); @@ -108,6 +118,9 @@ static struct qcom_icc_node *sm8150_osm_l3_nodes[] = { static const struct qcom_icc_desc sm8150_icc_osm_l3 = { .nodes = sm8150_osm_l3_nodes, .num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes), + .lut_row_size = OSM_LUT_ROW_SIZE, + .reg_freq_lut = OSM_REG_FREQ_LUT, + .reg_perf_state = OSM_REG_PERF_STATE, }; static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) @@ -138,7 +151,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) break; } - writel_relaxed(index, qp->base + REG_PERF_STATE); + writel_relaxed(index, qp->base + qp->reg_perf_state); return 0; } @@ -193,9 +206,15 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) return -ENODEV; } + desc = device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qp->reg_perf_state = desc->reg_perf_state; + for (i = 0; i < LUT_MAX_ENTRIES; i++) { - info = readl_relaxed(qp->base + REG_FREQ_LUT + - i * LUT_ROW_SIZE); + info = readl_relaxed(qp->base + desc->reg_freq_lut + + i * desc->lut_row_size); src = FIELD_GET(LUT_SRC, info); lval = FIELD_GET(LUT_L_VAL, info); if (src) @@ -214,10 +233,6 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) } qp->max_state = i; - desc = device_get_match_data(&pdev->dev); - if (!desc) - return -EINVAL; - qnodes = desc->nodes; num_nodes = desc->num_nodes; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SM8250 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + include/dt-bindings/interconnect/qcom,osm-l3.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index b6945c11eb46b..d6a95c3cb26f2 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc7180-osm-l3 - qcom,sdm845-osm-l3 - qcom,sm8150-osm-l3 + - qcom,sm8250-epss-l3 reg: maxItems: 1 diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h index 54858ff7674d7..61ef649ae5655 100644 --- a/include/dt-bindings/interconnect/qcom,osm-l3.h +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -9,4 +9,7 @@ #define MASTER_OSM_L3_APPS 0 #define SLAVE_OSM_L3 1 +#define MASTER_EPSS_L3_APPS 0 +#define SLAVE_EPSS_L3_SHARED 1 + #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Add Epoch Subsystem (EPSS) L3 interconnect provider support on SM8250 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- drivers/interconnect/qcom/osm-l3.c | 23 +++++++++++++++++++++++ drivers/interconnect/qcom/sm8250.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 27c9ece52efda..cbf4ef04491df 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -17,6 +17,7 @@ #include "sc7180.h" #include "sdm845.h" #include "sm8150.h" +#include "sm8250.h" #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) @@ -29,6 +30,11 @@ #define OSM_REG_FREQ_LUT 0x110 #define OSM_REG_PERF_STATE 0x920 +/* EPSS Register offsets */ +#define EPSS_LUT_ROW_SIZE 4 +#define EPSS_REG_FREQ_LUT 0x100 +#define EPSS_REG_PERF_STATE 0x320 + #define OSM_L3_MAX_LINKS 1 #define to_qcom_provider(_provider) \ @@ -123,6 +129,22 @@ static const struct qcom_icc_desc sm8150_icc_osm_l3 = { .reg_perf_state = OSM_REG_PERF_STATE, }; +DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3); +DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32); + +static struct qcom_icc_node *sm8250_epss_l3_nodes[] = { + [MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3, + [SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3, +}; + +static const struct qcom_icc_desc sm8250_icc_epss_l3 = { + .nodes = sm8250_epss_l3_nodes, + .num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_PERF_STATE, +}; + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -288,6 +310,7 @@ static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, + { .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match); diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h index 7eb6c709c30d1..b31fb431a20fc 100644 --- a/drivers/interconnect/qcom/sm8250.h +++ b/drivers/interconnect/qcom/sm8250.h @@ -158,5 +158,7 @@ #define SM8250_SLAVE_VSENSE_CTRL_CFG 147 #define SM8250_SNOC_CNOC_MAS 148 #define SM8250_SNOC_CNOC_SLV 149 +#define SM8250_MASTER_EPSS_L3_APPS 150 +#define SM8250_SLAVE_EPSS_L3 151 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Add Operation State Manager (OSM) L3 interconnect provider node on SM8150 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 0f6d84e8fd299..8563afd205ee9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,gcc-sm8150.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sm8150.h> #include <dt-bindings/thermal/thermal.h> @@ -1184,6 +1185,16 @@ apps_bcm_voter: bcm_voter { }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sm8150-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SM8250 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 73f02f712d035..2bcdb7a3b9fef 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-sm8250.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sm8250.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-aoss-qmp.h> @@ -2150,6 +2151,16 @@ apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; }; }; + + epss_l3: interconnect@18591000 { + compatible = "qcom,sm8250-epss-l3"; + reg = <0 0x18590000 0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; }; timer { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
On Sat, 01 Aug 2020 18:00:43 +0530, Sibi Sankar wrote:
> Add Operation State Manager (OSM) L3 interconnect provider binding on
> SM8150 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
On Sat, 01 Aug 2020 18:00:46 +0530, Sibi Sankar wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SM8250
> SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
> include/dt-bindings/interconnect/qcom,osm-l3.h | 3 +++
> 2 files changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
On 8/1/20 15:30, Sibi Sankar wrote: > Add Operation State Manager (OSM) L3 interconnect provider node on > SM8150 SoCs. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Acked-by: Georgi Djakov <georgi.djakov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 0f6d84e8fd299..8563afd205ee9 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -10,6 +10,7 @@ > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,gcc-sm8150.h> > +#include <dt-bindings/interconnect/qcom,osm-l3.h> > #include <dt-bindings/interconnect/qcom,sm8150.h> > #include <dt-bindings/thermal/thermal.h> > > @@ -1184,6 +1185,16 @@ apps_bcm_voter: bcm_voter { > }; > }; > > + osm_l3: interconnect@18321000 { > + compatible = "qcom,sm8150-osm-l3"; > + reg = <0 0x18321000 0 0x1400>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; > + clock-names = "xo", "alternate"; > + > + #interconnect-cells = <1>; > + }; > + > cpufreq_hw: cpufreq@18323000 { > compatible = "qcom,cpufreq-hw"; > reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, >