Re: [PATCH V2 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC

[Kathiravan T <quic_kathirav@quicinc.com>]

On 2/1/2023 11:15 AM, Kathiravan T wrote:
>
> On 2/1/2023 2:39 AM, Stephen Boyd wrote:
>> Quoting Kathiravan Thirumoorthy (2023-01-30 03:46:58)
>>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c 
>>> b/drivers/clk/qcom/gcc-ipq5332.c
>>> new file mode 100644
>>> index 000000000000..a8ce618bb81b
>>> --- /dev/null
>>> +++ b/drivers/clk/qcom/gcc-ipq5332.c
>>> @@ -0,0 +1,3954 @@
>> [...]
>>> +
>>> +static const struct clk_parent_data gcc_parent_data_xo = { .index = 
>>> DT_XO };
>>> +
>>> +static struct clk_alpha_pll gpll0_main = {
>> [...]
>>> +};
>>> +
>>> +static const struct parent_map gcc_parent_map_3[] = {
>>> +       { P_XO, 0 },
>>> +};
>>> +
>>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>> Isn't this the same as gcc_parent_data_xo?


Sorry missed in previous reply. Yeah correct. Will remove it and also 
check if any further duplicate entries.


>>
>>> +       { .index = DT_XO },
>>> +};
>>> +
>>> +static const struct parent_map gcc_parent_map_4[] = {
>>> +       { P_XO, 0 },
>>> +       { P_GPLL0_OUT_MAIN, 1 },
>>> +       { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
>>> +       { P_SLEEP_CLK, 6 },
>>> +};
>>> +
>>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>>> +       { .index = DT_XO },
>>> +       { .hw = &gpll0.clkr.hw },
>>> +       { .hw = &gpll0_div2.hw },
>> [..]
>>> +
>>> +static int gcc_ipq5332_probe(struct platform_device *pdev)
>>> +{
>>> +       struct regmap *regmap;
>>> +
>>> +       regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc);
>>> +       if (IS_ERR(regmap))
>>> +               return PTR_ERR(regmap);
>>> +
>>> +       return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap);
>> If you don't need to write anything in probe you can simply use
>> qcom_cc_probe().
>
>
> Thanks Stephen, will move to qcom_cc_probe in V3.
>
>