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From: Neil Armstrong <narmstrong@baylibre.com>
To: Jose Abreu <Jose.Abreu@synopsys.com>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: dri-devel@lists.freedesktop.org,
	laurent.pinchart+renesas@ideasonboard.com,
	kieran.bingham@ideasonboard.com,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] drm: bridge: dw-hdmi: Take input format from plat_data
Date: Mon, 6 Mar 2017 11:41:06 +0100	[thread overview]
Message-ID: <a69a053b-a026-37ca-ff3c-13bd88e3c3f6@baylibre.com> (raw)
In-Reply-To: <3cadc66c-9ca8-5658-0023-45ad68ca5939@synopsys.com>

On 03/03/2017 06:22 PM, Jose Abreu wrote:
> Hi Neil,
> 
> 
> On 03-03-2017 16:42, Neil Armstrong wrote:
>>
>> Sure, I was meaning the *input* format the controller receives from the
>> pixel encoder, I'm quite sure the format is strict.
>>
> 
> Hmm, not quite following you here. As far as the controller goes
> it supports the formats I mentioned:
>     -    8/10/12/16 bits RGB 4:4:4
>     -    8/10/12/16 bits YCbCr 4:4:4
>     -    8/10/12 bits YCbCr 4:2:2
>     -    8/10/12/16 bits YCbCr 4:2:0
> 
> As for the CSC it supports RGB 4:4:4 to/from YCbCr 4:4:4 or 4:2:2
> in every defined color depth.
> 
> So, everything except 4:2:0 (I had to check documentation, I
> though that CSC supported less formats).
> 
> Of course this is all limited by the implementation that HW team
> decides to choose.
> 
> Best regards,
> Jose Miguel Abreu
> 

Hi Jose,

Thanks for the clarifications.

I will try to add missing V4L formats

 - 8/10/12/16 bits RGB 4:4:4

MEDIA_BUS_FMT_RGB888_1X24
MEDIA_BUS_FMT_RGB101010_1X30 (to be added)
MEDIA_BUS_FMT_RGB121212_1X36 (to be added)
MEDIA_BUS_FMT_RGB161616_1X48 (to be added)

 - 8/10/12/16 bits YCbCr 4:4:4

MEDIA_BUS_FMT_YUV8_1X24
MEDIA_BUS_FMT_YUV10_1X30
MEDIA_BUS_FMT_YUV12_1X36 (to be added)
MEDIA_BUS_FMT_YUV16_1X48 (to be added)

 - 8/10/12 bits YCbCr 4:2:2

MEDIA_BUS_FMT_UYVY8_1X16
MEDIA_BUS_FMT_UYVY10_1X20
MEDIA_BUS_FMT_UYVY12_1X24

 - 8/10/12/16 bits YCbCr 4:2:0

Jose, how is supposed to be transmitted 4:2:0 over the controller ?

Amlogic uses clock doubling to transmit 4:2:0 in CrYCb format.

I assume, the transmission is in YYUYYV format in 2x clock.

So the formats should be (aligned on the MEDIA_BUS_FMT_YUYV8_1_5X8) :

MEDIA_BUS_FMT_YUYV8_1_1X24 (to be added)
MEDIA_BUS_FMT_YUYV10_1_1X30 (to be added)
MEDIA_BUS_FMT_YUYV12_1_1X36 (to be added)
MEDIA_BUS_FMT_YUYV16_1_1X48 (to be added)

to have the following transmissions scheme :

uuuuuuuu/yyyyyyyy/yyyyyyyy
vvvvvvvv/yyyyyyyy/yyyyyyyy

Can you confirm this ?

Neil

  reply	other threads:[~2017-03-06 10:42 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-02 15:29 [PATCH v2 0/2] drm: bridge: dw-hdmi: Add support for Custom PHYs Neil Armstrong
2017-03-02 15:29 ` [PATCH v2 1/2] drm: bridge: dw-hdmi: Take input format from plat_data Neil Armstrong
2017-03-02 15:45   ` Laurent Pinchart
2017-03-03 11:31     ` Neil Armstrong
2017-03-03 16:39       ` Jose Abreu
2017-03-03 16:42         ` Neil Armstrong
2017-03-03 17:22           ` Jose Abreu
2017-03-06 10:41             ` Neil Armstrong [this message]
2017-03-06 12:17               ` Jose Abreu
2017-03-06 12:39                 ` Neil Armstrong
2017-03-02 15:29 ` [PATCH v2 2/2] drm: bridge: Move HPD handling to PHY operations Neil Armstrong
2017-03-02 16:18   ` Laurent Pinchart
2017-03-03  9:07     ` Neil Armstrong
2017-03-03 10:05       ` Jose Abreu
2017-03-03 12:16         ` Laurent Pinchart

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