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Tue, 19 Nov 2019 08:04:14 +0000 (UTC) Received: from [10.36.116.37] (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E39B75F765; Tue, 19 Nov 2019 08:04:11 +0000 (UTC) Subject: Re: [PATCH v2 04/10] iommu/vt-d: Match CPU and IOMMU paging mode To: Lu Baolu , Jacob Pan Cc: iommu@lists.linux-foundation.org, LKML , Joerg Roedel , David Woodhouse , "Tian, Kevin" , Raj Ashok , Yi Liu References: <1574106153-45867-1-git-send-email-jacob.jun.pan@linux.intel.com> <1574106153-45867-5-git-send-email-jacob.jun.pan@linux.intel.com> <601ca9c3-9f83-3d95-8d26-d4f46eee82ba@redhat.com> <20191118135238.49f5d957@jacob-builder> From: Auger Eric Message-ID: Date: Tue, 19 Nov 2019 09:04:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 90Y80ZSfNmGJW1iF4g-Hpw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lu, Jacob, On 11/19/19 4:06 AM, Lu Baolu wrote: > Hi Eric and Jacob, >=20 > On 11/19/19 5:52 AM, Jacob Pan wrote: >> On Mon, 18 Nov 2019 21:55:03 +0100 >> Auger Eric wrote: >> >>> Hi Jacob, >>> >>> On 11/18/19 8:42 PM, Jacob Pan wrote: >>>> When setting up first level page tables for sharing with CPU, we >>>> need to ensure IOMMU can support no less than the levels supported >>>> by the CPU. >>>> It is not adequate, as in the current code, to set up 5-level paging >>>> in PASID entry First Level Paging Mode(FLPM) solely based on CPU. >>>> >>>> Fixes: 437f35e1cd4c8 ("iommu/vt-d: Add first level page table >>>> interface") >>>> Signed-off-by: Jacob Pan >>>> Acked-by: Lu Baolu >>>> --- >>>> =C2=A0 drivers/iommu/intel-pasid.c | 12 ++++++++++-- >>>> =C2=A0 1 file changed, 10 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/iommu/intel-pasid.c >>>> b/drivers/iommu/intel-pasid.c index 040a445be300..e7cb0b8a7332 >>>> 100644 --- a/drivers/iommu/intel-pasid.c >>>> +++ b/drivers/iommu/intel-pasid.c >>>> @@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct >>>> intel_iommu *iommu, } >>>> =C2=A0 =C2=A0 #ifdef CONFIG_X86 >>>> -=C2=A0=C2=A0=C2=A0 if (cpu_feature_enabled(X86_FEATURE_LA57)) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pasid_set_flpm(pte, 1); >>>> +=C2=A0=C2=A0=C2=A0 /* Both CPU and IOMMU paging mode need to match */ >>>> +=C2=A0=C2=A0=C2=A0 if (cpu_feature_enabled(X86_FEATURE_LA57)) { >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (cap_5lp_support(iommu-= >cap)) { >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pa= sid_set_flpm(pte, 1); >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else { >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pr= _err("VT-d has no 5-level paging support >>>> for CPU\n"); >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pa= sid_clear_entry(pte); >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 re= turn -EINVAL; >>> Can it happen? If I am not wrong intel_pasid_setup_first_level() only >>> seems to be called from intel_svm_bind_mm which now checks the >>> SVM_CAPABLE flag. >>> >> You are right, this check is not needed any more. I will drop the patch. >>> Thanks >=20 > I'd suggest to keep this. This helper is not only for svm, although > currently svm is the only caller. For first level pasid setup, let's > set an assumption that hardware should never report mismatching paging > modes, this is helpful especially when running vIOMMU in VM guests. OK. So maybe just add the rationale in the commit message? Thanks Eric >=20 > Best regards, > baolu >=20