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[77.136.35.189]) by smtp.googlemail.com with ESMTPSA id 134-v6sm5450488wmp.6.2018.11.22.05.23.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 05:23:43 -0800 (PST) Subject: Re: [RFC PATCH v3 07/17] clocksource: sun4i: add a compatible for suniv To: Mesih Kilinc , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Maxime Ripard , Chen-Yu Tsai , Russell King , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby References: <60bc70fc43743f664de76abf3ab0a01cd7924458.1542824904.git.mesihkilinc@gmail.com> From: Daniel Lezcano Message-ID: Date: Thu, 22 Nov 2018 14:23:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <60bc70fc43743f664de76abf3ab0a01cd7924458.1542824904.git.mesihkilinc@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/11/2018 19:30, Mesih Kilinc wrote: > The suniv (new F-series) chip has a timer with less functionality than > the A10 timer, e.g. it has only 3 channels. > > Add a new compatible for it. As we didn't use the extra channels on A10 > either now, the code needn't to be changed. > > The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer. > > Register sun4i_timer as sched_clock on it. > > Signed-off-by: Mesih Kilinc Acked-by: Daniel Lezcano > --- > drivers/clocksource/sun4i_timer.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c > index 6e0180a..65f38f6 100644 > --- a/drivers/clocksource/sun4i_timer.c > +++ b/drivers/clocksource/sun4i_timer.c > @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) > */ > if (of_machine_is_compatible("allwinner,sun4i-a10") || > of_machine_is_compatible("allwinner,sun5i-a13") || > - of_machine_is_compatible("allwinner,sun5i-a10s")) > + of_machine_is_compatible("allwinner,sun5i-a10s") || > + of_machine_is_compatible("allwinner,suniv-f1c100s")) > sched_clock_register(sun4i_timer_sched_read, 32, > timer_of_rate(&to)); > > @@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node) > } > TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", > sun4i_timer_init); > +TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer", > + sun4i_timer_init); > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog