From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F47BC433E8 for ; Fri, 19 Mar 2021 16:25:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01E056197D for ; Fri, 19 Mar 2021 16:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230259AbhCSQYh (ORCPT ); Fri, 19 Mar 2021 12:24:37 -0400 Received: from mga14.intel.com ([192.55.52.115]:1251 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbhCSQYM (ORCPT ); Fri, 19 Mar 2021 12:24:12 -0400 IronPort-SDR: By9IQQ4GaUfFcSoTvRrzC60BVrkzdJGkOhTeFRFdYC/ezkXqaQVnKtdyYqXawwOadw4exin6CX Lvwj5WELPkYw== X-IronPort-AV: E=McAfee;i="6000,8403,9928"; a="189302577" X-IronPort-AV: E=Sophos;i="5.81,262,1610438400"; d="scan'208";a="189302577" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2021 09:24:12 -0700 IronPort-SDR: o3DGciW8KGoQICX8T/gkyV99iraCaufszZ2fID2FohW8nHAIPwzfPXYALNpFGfDLzwX7vKhd+J eiKXa2vfuyug== X-IronPort-AV: E=Sophos;i="5.81,262,1610438400"; d="scan'208";a="603189058" Received: from yyu32-mobl1.amr.corp.intel.com (HELO [10.212.100.40]) ([10.212.100.40]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2021 09:24:11 -0700 Subject: Re: [PATCH v23 00/28] Control-flow Enforcement: Shadow Stack To: Ingo Molnar Cc: Peter Zijlstra , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang , Pengfei Xu , Haitao Huang References: <20210316151054.5405-1-yu-cheng.yu@intel.com> <20210316211552.GU4746@worktop.programming.kicks-ass.net> <90e453ee-377b-0342-55f9-9412940262f2@intel.com> <20210317091800.GA1461644@gmail.com> From: "Yu, Yu-cheng" Message-ID: Date: Fri, 19 Mar 2021 09:24:10 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: <20210317091800.GA1461644@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/17/2021 2:18 AM, Ingo Molnar wrote: > > * Yu, Yu-cheng wrote: > >> On 3/16/2021 2:15 PM, Peter Zijlstra wrote: >>> On Tue, Mar 16, 2021 at 08:10:26AM -0700, Yu-cheng Yu wrote: >>>> Control-flow Enforcement (CET) is a new Intel processor feature that blocks >>>> return/jump-oriented programming attacks. Details are in "Intel 64 and >>>> IA-32 Architectures Software Developer's Manual" [1]. >>>> >>>> CET can protect applications and the kernel. This series enables only >>>> application-level protection, and has three parts: >>>> >>>> - Shadow stack [2], >>>> - Indirect branch tracking [3], and >>>> - Selftests [4]. >>> >>> CET is marketing; afaict SS and IBT are 100% independent and there's no >>> reason what so ever to have them share any code, let alone a Kconfig >>> knob. >> >> We used to have shadow stack and ibt under separate Kconfig options, but in >> a few places they actually share same code path, such as the XSAVES >> supervisor states and ELF header for example. Anyways I will be happy to >> make changes again if there is agreement. > > I was look at: > > x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states > > didn't see any IBT logic - it's essentially all shadow stack state. > > Which is not surprising, forward call edge integrity protection (IBT) > requires very little state, does it? > > With IBT there's no nesting, no stack - the IBT state machine > basically requires the next instruction to be and ENDBR instruction, > and that's essentially it, right? > > Thanks, > > Ingo > Yes, that is it. The CET_WAIT_ENDBR bit is the status of IBT state machine. There are a few bits in MSR_IA32_U_CET controlling how IBT works, but those are not status. Yu-cheng