From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: ACJfBovBASjoGrf0nUlvCwqhXkvBsvJPDJHGVksF3rEdQ7RnDrZRw21ybDnILXgRqZ0y5Y4l39Y7 ARC-Seal: i=1; a=rsa-sha256; t=1516212514; cv=none; d=google.com; s=arc-20160816; b=x1sc6Ub/pfAvGEAu/ZKxv+cwiQktaXPZYqbbVnSQNOdNQOcha99ozTXDaH19lL2Q3Z x2eVKpwV6YOCDJnqa3yCkEqoGk0sAjAhqzkvVoihVXKW8JUr2qTjL2S76xMFyn98l4jA qKgQeFGqdoombu0o+bVLxK5+mRRaC9Q8DFQaLF3a3b2/QMRk5T0Pj9tzbAEZaOIaZ2Hp mNmJt2KRBMC6CuFTFQcbrbPYn3Eqz1nFng+xU1tPFTiMZ4bD7I5a+FzqIxNEowUw8MOY N9lg43OxZtSxuX0h7h6YnIjDj7bICaGG/pgy2TylUIkX0HHTX1bhdtW0G8h9yQ/kMcMD Gmgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:content-language:in-reply-to:mime-version :user-agent:date:message-id:organization:from:references:to:subject :cc:arc-authentication-results; bh=R59jG3CuAco25FvniLSCWahkpFIYGq51q2DE8oi/n+4=; b=mNeqTgcp/gnsFUz56iQUkTWHODeQpn/GXSB82K2m4x2YVpSr56Dzskh9r116hpkhbQ UM4lxDzH6mV18E28Y4TMMS5o1TIK42Rcgay8QklwXal1qEptaLg2cKe9iUekA1JlkjbG Hta9pDwPacOkqdglQ8LbXNKEzivlaz68HnHukl3KSaZhGCUgqhY6QKbVeouiR8/s3FjS Q98vBKNOp//JqilDhJNG4rY1lj6g5f61ZTg7ajabqfLmiIzj3JQ3jg3XELJOiYA36rKM vEZQX8YIDCXPC1l+S2IBOe4WYFI3zIS38osaOVCKR/BRVQbNj9HURgVM4UenN7ct5CwA rLyg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of sudeep.holla@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=sudeep.holla@arm.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of sudeep.holla@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=sudeep.holla@arm.com Cc: Sudeep Holla , jeremy.linton@arm.com, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, Will Deacon , catalin.marinas@arm.com, Greg KH , viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, vkilari@codeaurora.org, morten.rasmussen@arm.com, albert@sifive.com Subject: Re: [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early To: Palmer Dabbelt References: From: Sudeep Holla Organization: ARM Message-ID: Date: Wed, 17 Jan 2018 18:08:27 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1589436997037379564?= X-GMAIL-MSGID: =?utf-8?q?1589864053956294726?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: (Sorry, somehow I missed this email until I saw Jeremy's reply today) On 15/01/18 16:07, Palmer Dabbelt wrote: > On Mon, 15 Jan 2018 04:33:38 PST (-0800), sudeep.holla@arm.com wrote: >> On Fri, Jan 12, 2018 at 06:59:10PM -0600, Jeremy Linton wrote: >>> The original intent in cacheinfo was that an architecture >>> specific populate_cache_leaves() would probe the hardware >>> and then cache_shared_cpu_map_setup() and >>> cache_override_properties() would provide firmware help to >>> extend/expand upon what was probed. Arm64 was really >>> the only architecture that was working this way, and >>> with the removal of most of the hardware probing logic it >>> became clear that it was possible to simplify the logic a bit. >>> >>> This patch combines the walk of the DT nodes with the >>> code updating the cache size/line_size and nr_sets. >>> cache_override_properties() (which was DT specific) is >>> then removed. The result is that cacheinfo.of_node is >>> no longer used as a temporary place to hold DT references >>> for future calls that update cache properties. That change >>> helps to clarify its one remaining use (matching >>> cacheinfo nodes that represent shared caches) which >>> will be used by the ACPI/PPTT code in the following patches. >>> >>> Cc: Palmer Dabbelt >>> Cc: Albert Ou >>> Signed-off-by: Jeremy Linton >>> --- >>>  arch/riscv/kernel/cacheinfo.c |  1 + >>>  drivers/base/cacheinfo.c      | 65 >>> +++++++++++++++++++------------------------ >>>  include/linux/cacheinfo.h     |  1 + >>>  3 files changed, 31 insertions(+), 36 deletions(-) >>> >>> diff --git a/arch/riscv/kernel/cacheinfo.c >>> b/arch/riscv/kernel/cacheinfo.c >>> index 10ed2749e246..6f4500233cf8 100644 >>> --- a/arch/riscv/kernel/cacheinfo.c >>> +++ b/arch/riscv/kernel/cacheinfo.c >>> @@ -30,6 +30,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, >>>          CACHE_WRITE_BACK >>>          | CACHE_READ_ALLOCATE >>>          | CACHE_WRITE_ALLOCATE; >>> +    cache_of_set_props(this_leaf, node); >> >> This may be necessary but can it be done as later patch ? So far nothing >> is added that may break riscv IIUC. >> >> Palmer, Albert, >> >> Can you confirm ? Also, as I see we can thin down arch specific >> implementation on riscv if it's just using DT like ARM64. Sorry if >> I am missing to see something, so thought of checking. >> >> [...] > > Sorry, I guess I'm a bit confused as to what's going on here.  RISC-V > uses device tree on all Linux systems. > Good. By thin down, I was thinking of moving the init_cache_level and populate_cache_leaves implementation of riscv to generic weak function under CONFIG_OF. You may even endup deleting riscv cacheinfo.c Just a thought, sorry for not being clear earlier. -- Regards, Sudeep