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From: Adrian Hunter <adrian.hunter@intel.com>
To: Mingbo Zhang <whensungoes@gmail.com>, x86@kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Masami Hiramatsu <mhiramat@kernel.org>,
	Arnaldo Carvalho de Melo <acme@redhat.com>,
	Andi Kleen <ak@linux.intel.com>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	linux-kernel@vger.kernel.org, Yu-cheng Yu <yu-cheng.yu@intel.com>
Subject: Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions
Date: Tue, 3 Mar 2020 09:20:39 +0200	[thread overview]
Message-ID: <a9039e7c-db8f-ddda-8298-b89b66b65408@intel.com> (raw)
In-Reply-To: <931d8779-8b77-b75f-bb3a-ee2f9d75f149@intel.com>

On 3/03/20 9:17 am, Adrian Hunter wrote:
> On 3/03/20 6:50 am, Mingbo Zhang wrote:
>> Intel CET instructions are not described in the Intel SDM. When trying to
>> get the instruction length, the following instructions get wrong (missing
>> ModR/M byte).
>>
>> RDSSPD r32
>> RSDDPQ r64
>> ENDBR32
>> ENDBR64
>> WRSSD r/m32, r32
>> WRSSQ r/m64, r64
>>
>> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is
>> described in SDM as Reserved-NOP with no encoding characters, and got an
>> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot.
> 
> We have patches for that:
> 
> 	https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/
> 
> But they have not yet been applied.  Arnaldo, could you take them?
> 

For reference:

Subject: [PATCH 0/2] Introduce Control-flow Enforcement opcodes
Date: Tue,  4 Feb 2020 09:14:23 -0800
Message-ID: <20200204171425.28073-1-yu-cheng.yu@intel.com> (raw)

Control-flow Enforcement (CET) introduces 10 new instructions [1].  Add
them to the opcode map.  This series has been separated from the CET
patches [2] for ease of review.

[1] Detailed information on CET can be found in "Intel 64 and IA-32
    Architectures Software Developer's Manual":

    https://software.intel.com/en-us/download/intel-64-and-ia-32-
    architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4

[2] CET patches:

    https://lkml.kernel.org/r/20190813205225.12032-1-yu-cheng.yu@intel.com/
    https://lkml.kernel.org/r/20190813205359.12196-1-yu-cheng.yu@intel.com/

Adrian Hunter (1):
  x86/insn: perf tools: Add CET instructions to the new instructions
    test

Yu-cheng Yu (1):
  x86/insn: Add Control-flow Enforcement (CET) instructions to the
    opcode map

 arch/x86/lib/x86-opcode-map.txt              |  17 +-
 tools/arch/x86/lib/x86-opcode-map.txt        |  17 +-
 tools/perf/arch/x86/tests/insn-x86-dat-32.c  | 112 +++++++++
 tools/perf/arch/x86/tests/insn-x86-dat-64.c  | 196 +++++++++++++++
 tools/perf/arch/x86/tests/insn-x86-dat-src.c | 236 +++++++++++++++++++
 5 files changed, 566 insertions(+), 12 deletions(-)

  reply	other threads:[~2020-03-03  7:21 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-03  4:50 [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions Mingbo Zhang
2020-03-03  7:17 ` Adrian Hunter
2020-03-03  7:20   ` Adrian Hunter [this message]
2020-03-16  7:10   ` Adrian Hunter
2020-03-25  6:10     ` Adrian Hunter
2020-03-26  1:31 ` Masami Hiramatsu
2020-03-26  5:09   ` Adrian Hunter
2020-03-26 13:55     ` Arnaldo Carvalho de Melo
2020-03-26 14:19       ` Hunter, Adrian
2020-03-26 14:57         ` Arnaldo Carvalho de Melo
2020-03-26 15:01           ` Arnaldo Carvalho de Melo
2020-03-26 17:36             ` Adrian Hunter
2020-03-26 20:35               ` Arnaldo Carvalho de Melo

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