From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA767C07E95 for ; Fri, 2 Jul 2021 22:07:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 903A561449 for ; Fri, 2 Jul 2021 22:07:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234522AbhGBWKU (ORCPT ); Fri, 2 Jul 2021 18:10:20 -0400 Received: from mga17.intel.com ([192.55.52.151]:15309 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233176AbhGBWIp (ORCPT ); Fri, 2 Jul 2021 18:08:45 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10033"; a="189168415" X-IronPort-AV: E=Sophos;i="5.83,320,1616482800"; d="scan'208";a="189168415" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2021 15:05:32 -0700 X-IronPort-AV: E=Sophos;i="5.83,320,1616482800"; d="scan'208";a="642814893" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2021 15:05:31 -0700 From: isaku.yamahata@intel.com To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , erdemaktas@google.com, Connor Kuehl , Sean Christopherson , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Kai Huang Subject: [RFC PATCH v2 64/69] cpu/hotplug: Document that TDX also depends on booting CPUs once Date: Fri, 2 Jul 2021 15:05:10 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kai Huang Add a comment to explain that TDX also depends on booting logical CPUs at least once. TDSYSINITLP must be run on all CPUs, even software disabled CPUs in the -nosmt case. Fortunately, current SMT handling for #MC already supports booting all CPUs once; the to-be-disabled sibling is booted once (and later put into deep C-state to honor SMT=off) to allow the init code to set CR4.MCE and avoid an unwanted shutdown on a broadcasted MCE. Signed-off-by: Kai Huang Signed-off-by: Isaku Yamahata --- kernel/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/kernel/cpu.c b/kernel/cpu.c index e538518556f4..58377a03e9d6 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -446,6 +446,10 @@ static inline bool cpu_smt_allowed(unsigned int cpu) * that the init code can get a chance to set CR4.MCE on each * CPU. Otherwise, a broadcasted MCE observing CR4.MCE=0b on any * core will shutdown the machine. + * + * Intel TDX also requires running TDH_SYS_LP_INIT on all logical CPUs + * during boot, booting all CPUs once allows TDX to play nice with + * 'nosmt'. */ return !cpumask_test_cpu(cpu, &cpus_booted_once_mask); } -- 2.25.1