* [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver
2020-02-07 20:37 [PATCH v2 0/4] platform/chrome: Add Type C connector class driver Prashant Malani
@ 2020-02-07 20:37 ` Prashant Malani
2020-02-11 10:28 ` Enric Balletbo i Serra
2020-02-11 23:25 ` Rob Herring
2020-02-07 20:37 ` [PATCH v2 2/4] platform/chrome: Add Type C connector class driver Prashant Malani
` (2 subsequent siblings)
3 siblings, 2 replies; 12+ messages in thread
From: Prashant Malani @ 2020-02-07 20:37 UTC (permalink / raw)
To: linux-kernel
Cc: heikki.krogerus, enric.balletbo, bleung, Prashant Malani,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland, Rob Herring
Some Chrome OS devices with Embedded Controllers (EC) can read and
modify Type C port state.
Add an entry in the DT Bindings documentation that lists out the logical
device and describes the relevant port information, to be used by the
corresponding driver.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
---
Changes in v2:
- No changes. Patch first introduced in v2 of series.
.../bindings/chrome/google,cros-ec-typec.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
new file mode 100644
index 00000000000000..46ebcbe76db3c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Chrome OS EC(Embedded Controller) Type C port driver.
+
+maintainers:
+ - Benson Leung <bleung@chromium.org>
+ - Prashant Malani <pmalani@chromium.org>
+
+description:
+ Chrome OS devices have an Embedded Controller(EC) which has access to
+ Type C port state. This node is intended to allow the host to read and
+ control the Type C ports. The node for this device should be under a
+ cros-ec node like google,cros-ec-spi.
+
+properties:
+ compatible:
+ const: google,cros-ec-typec
+
+ port:
+ description: A node that represents a physical Type C port on the
+ device.
+ type: object
+ properties:
+ port-number:
+ description: The number used by the Chrome OS EC to identify
+ this type C port.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ power-role:
+ description: Determines the power role that the Type C port will
+ adopt.
+ oneOf:
+ - items:
+ - const: sink
+ - const: source
+ - const: dual
+ data-role:
+ description: Determines the data role that the Type C port will
+ adopt.
+ oneOf:
+ - items:
+ - const: host
+ - const: device
+ - const: dual
+ try-power-role:
+ description: Determines the preferred power role of the Type C port.
+ oneOf:
+ - items:
+ - const: sink
+ - const: source
+ - const: dual
+
+ required:
+ - port-number
+ - power-role
+ - data-role
+ - try-power-role
+
+required:
+ - compatible
+ - port
+
+examples:
+ - |+
+ typec {
+ compatible = "google,cros-ec-typec";
+
+ port@0 {
+ port-number = <0>;
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "source";
+ };
+ };
--
2.25.0.341.g760bfbb309-goog
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver
2020-02-07 20:37 ` [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver Prashant Malani
@ 2020-02-11 10:28 ` Enric Balletbo i Serra
[not found] ` <CACeCKac-OjvCLZ4FefsGbH9JR_suB3nL5CVLa_N0o9qnSqi3-g@mail.gmail.com>
2020-02-11 23:25 ` Rob Herring
1 sibling, 1 reply; 12+ messages in thread
From: Enric Balletbo i Serra @ 2020-02-11 10:28 UTC (permalink / raw)
To: Prashant Malani, linux-kernel
Cc: heikki.krogerus, bleung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland, Rob Herring
Hi Prashant,
On 7/2/20 21:37, Prashant Malani wrote:
> Some Chrome OS devices with Embedded Controllers (EC) can read and
> modify Type C port state.
>
> Add an entry in the DT Bindings documentation that lists out the logical
> device and describes the relevant port information, to be used by the
> corresponding driver.
>
> Signed-off-by: Prashant Malani <pmalani@chromium.org>
> ---
>
> Changes in v2:
> - No changes. Patch first introduced in v2 of series.
>
> .../bindings/chrome/google,cros-ec-typec.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
>
> diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
> new file mode 100644
> index 00000000000000..46ebcbe76db3c2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0
I think that Google is fine with the dual licensing here. Would be good if this
can be (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Chrome OS EC(Embedded Controller) Type C port driver.
> +
> +maintainers:
> + - Benson Leung <bleung@chromium.org>
> + - Prashant Malani <pmalani@chromium.org>
> +
> +description:
> + Chrome OS devices have an Embedded Controller(EC) which has access to
> + Type C port state. This node is intended to allow the host to read and
> + control the Type C ports. The node for this device should be under a
> + cros-ec node like google,cros-ec-spi.
> +
> +properties:
> + compatible:
> + const: google,cros-ec-typec
> +
> + port:
> + description: A node that represents a physical Type C port on the
> + device.
> + type: object
> + properties:
> + port-number:
> + description: The number used by the Chrome OS EC to identify
> + this type C port.
> + $ref: /schemas/types.yaml#/definitions/uint32
Any range of values allowed? 0 is okay?
> + power-role:
Sorry if this question is silly, aren't this and below properties the same as
provided by usb-connector? Can't this be usb-c-connector?
Documentation/devicetree/bindings/connector/usb-connector.txt
> + description: Determines the power role that the Type C port will
> + adopt.
> + oneOf:
> + - items:
> + - const: sink
> + - const: source
> + - const: dual
> + data-role:
> + description: Determines the data role that the Type C port will
> + adopt.
> + oneOf:
> + - items:
> + - const: host
> + - const: device
> + - const: dual
> + try-power-role:
> + description: Determines the preferred power role of the Type C port.
> + oneOf:
> + - items:
> + - const: sink
> + - const: source
> + - const: dual
> +
> + required:
> + - port-number
> + - power-role
> + - data-role
> + - try-power-role
> +
> +required:
> + - compatible
> + - port
> +
> +examples:
> + - |+
Rob can confirm, but I think is a good practice add the parent node, so add the
cros-ec-spi node here?
> + typec {
> + compatible = "google,cros-ec-typec";
> +
> + port@0 {
You can run:
make dt_binding_check DT_SCHEMA_FILES=<...>/chrome/google,cros-ec-typec.yaml
And you'll get an error:
typec: 'port' is a required property
> + port-number = <0>;
> + power-role = "dual";
> + data-role = "dual";
> + try-power-role = "source";
> + };
> + };
>
Thanks,
Enric
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver
2020-02-07 20:37 ` [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver Prashant Malani
2020-02-11 10:28 ` Enric Balletbo i Serra
@ 2020-02-11 23:25 ` Rob Herring
2020-02-12 15:53 ` Heikki Krogerus
1 sibling, 1 reply; 12+ messages in thread
From: Rob Herring @ 2020-02-11 23:25 UTC (permalink / raw)
To: Prashant Malani
Cc: linux-kernel, heikki.krogerus, Enric Balletbo i Serra,
Benson Leung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland
On Fri, Feb 7, 2020 at 2:39 PM Prashant Malani <pmalani@chromium.org> wrote:
>
> Some Chrome OS devices with Embedded Controllers (EC) can read and
> modify Type C port state.
>
> Add an entry in the DT Bindings documentation that lists out the logical
> device and describes the relevant port information, to be used by the
> corresponding driver.
>
> Signed-off-by: Prashant Malani <pmalani@chromium.org>
> ---
>
> Changes in v2:
> - No changes. Patch first introduced in v2 of series.
>
> .../bindings/chrome/google,cros-ec-typec.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
>
> diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
> new file mode 100644
> index 00000000000000..46ebcbe76db3c2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Chrome OS EC(Embedded Controller) Type C port driver.
> +
> +maintainers:
> + - Benson Leung <bleung@chromium.org>
> + - Prashant Malani <pmalani@chromium.org>
> +
> +description:
> + Chrome OS devices have an Embedded Controller(EC) which has access to
> + Type C port state. This node is intended to allow the host to read and
> + control the Type C ports. The node for this device should be under a
> + cros-ec node like google,cros-ec-spi.
> +
> +properties:
> + compatible:
> + const: google,cros-ec-typec
> +
> + port:
> + description: A node that represents a physical Type C port on the
> + device.
> + type: object
> + properties:
> + port-number:
> + description: The number used by the Chrome OS EC to identify
> + this type C port.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + power-role:
> + description: Determines the power role that the Type C port will
> + adopt.
> + oneOf:
> + - items:
> + - const: sink
> + - const: source
> + - const: dual
> + data-role:
> + description: Determines the data role that the Type C port will
> + adopt.
> + oneOf:
> + - items:
> + - const: host
> + - const: device
> + - const: dual
> + try-power-role:
> + description: Determines the preferred power role of the Type C port.
> + oneOf:
> + - items:
> + - const: sink
> + - const: source
> + - const: dual
> +
> + required:
> + - port-number
> + - power-role
> + - data-role
> + - try-power-role
> +
> +required:
> + - compatible
> + - port
> +
> +examples:
> + - |+
> + typec {
> + compatible = "google,cros-ec-typec";
> +
> + port@0 {
'port' is reserved for OF graph binding which this is not.
> + port-number = <0>;
> + power-role = "dual";
> + data-role = "dual";
> + try-power-role = "source";
These are usb-connector binding properties, but this is not a
usb-connector node. However, I think it should be. The main thing to
work out seems to be have multiple connectors.
With your binding, how does one associate the USB host controller with
each port/connector? That's a solved problem with the connector
binding.
Rob
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver
2020-02-11 23:25 ` Rob Herring
@ 2020-02-12 15:53 ` Heikki Krogerus
0 siblings, 0 replies; 12+ messages in thread
From: Heikki Krogerus @ 2020-02-12 15:53 UTC (permalink / raw)
To: Rob Herring
Cc: Prashant Malani, linux-kernel, heikki.krogerus,
Enric Balletbo i Serra, Benson Leung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland
Hi Rob,
On Tue, Feb 11, 2020 at 05:25:13PM -0600, Rob Herring wrote:
> > +examples:
> > + - |+
> > + typec {
> > + compatible = "google,cros-ec-typec";
> > +
> > + port@0 {
>
> 'port' is reserved for OF graph binding which this is not.
>
> > + port-number = <0>;
> > + power-role = "dual";
> > + data-role = "dual";
> > + try-power-role = "source";
>
> These are usb-connector binding properties, but this is not a
> usb-connector node. However, I think it should be. The main thing to
> work out seems to be have multiple connectors.
>
> With your binding, how does one associate the USB host controller with
> each port/connector? That's a solved problem with the connector
> binding.
It looks like OF graph is required to be used for that. The plan was
actually to propose that we use device properties "usb2-port" and
"usb3-port" that directly reference the port nodes under the USB host
controller, but I guess that's too late for that.
OF graph creates one problem. We are going to need to identify the
endpoints somehow in the USB Type-C drivers, so how do we know which
endpoint is for example the USB2 port, which is USB3, which is
DisplayPort, etc?
Does the remote-endpoint parent need to have a specific compatible
property, like the USB2 port needs to have compatible = "usb2-port"
and so on?
thanks,
--
heikki
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/4] platform/chrome: Add Type C connector class driver
2020-02-07 20:37 [PATCH v2 0/4] platform/chrome: Add Type C connector class driver Prashant Malani
2020-02-07 20:37 ` [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver Prashant Malani
@ 2020-02-07 20:37 ` Prashant Malani
2020-02-11 11:26 ` Enric Balletbo i Serra
2020-02-12 16:53 ` Heikki Krogerus
2020-02-07 20:37 ` [PATCH v2 3/4] platform/chrome: typec: Get PD_CONTROL cmd version Prashant Malani
2020-02-07 20:37 ` [PATCH v2 4/4] platform/chrome: typec: Update port info from EC Prashant Malani
3 siblings, 2 replies; 12+ messages in thread
From: Prashant Malani @ 2020-02-07 20:37 UTC (permalink / raw)
To: linux-kernel
Cc: heikki.krogerus, enric.balletbo, bleung, Prashant Malani,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland, Rob Herring
Add a driver to implement the Type C connector class for Chrome OS
devices with ECs (Embedded Controllers).
The driver relies on firmware device specifications for various port
attributes. On ACPI platforms, this is specified using the logical
device with HID GOOG0014. On DT platforms, this is specified using the
DT node with compatible string "google,cros-ec-typec".
This patch reads the device FW node and uses the port attributes to
register the typec ports with the Type C connector class framework, but
doesn't do much else.
Subsequent patches will add more functionality to the driver, including
obtaining current port information (polarity, vconn role, current power
role etc.) after querying the EC.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
---
Changes in v2:
- Updated Kconfig to default to MFD_CROS_EC_DEV.
- Fixed code comments.
- Moved get_num_ports() code into probe().
- Added module author.
drivers/platform/chrome/Kconfig | 11 ++
drivers/platform/chrome/Makefile | 1 +
drivers/platform/chrome/cros_ec_typec.c | 218 ++++++++++++++++++++++++
3 files changed, 230 insertions(+)
create mode 100644 drivers/platform/chrome/cros_ec_typec.c
diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
index 5f57282a28da00..2320a4f0d93019 100644
--- a/drivers/platform/chrome/Kconfig
+++ b/drivers/platform/chrome/Kconfig
@@ -214,6 +214,17 @@ config CROS_EC_SYSFS
To compile this driver as a module, choose M here: the
module will be called cros_ec_sysfs.
+config CROS_EC_TYPEC
+ tristate "ChromeOS EC Type-C Connector Control"
+ depends on MFD_CROS_EC_DEV && TYPEC
+ default MFD_CROS_EC_DEV
+ help
+ If you say Y here, you get support for accessing Type C connector
+ information from the Chrome OS EC.
+
+ To compile this driver as a module, choose M here: the module will be
+ called cros_ec_typec.
+
config CROS_USBPD_LOGGER
tristate "Logging driver for USB PD charger"
depends on CHARGER_CROS_USBPD
diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
index aacd5920d8a180..caf2a9cdb5e6d1 100644
--- a/drivers/platform/chrome/Makefile
+++ b/drivers/platform/chrome/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_ISHTP) += cros_ec_ishtp.o
obj-$(CONFIG_CROS_EC_RPMSG) += cros_ec_rpmsg.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o
+obj-$(CONFIG_CROS_EC_TYPEC) += cros_ec_typec.o
obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
obj-$(CONFIG_CROS_EC_PROTO) += cros_ec_proto.o cros_ec_trace.o
obj-$(CONFIG_CROS_KBD_LED_BACKLIGHT) += cros_kbd_led_backlight.o
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
new file mode 100644
index 00000000000000..8374ccfe784f3b
--- /dev/null
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2020 Google LLC
+ *
+ * This driver provides the ability to view and manage Type C ports through the
+ * Chrome OS EC.
+ */
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_data/cros_ec_commands.h>
+#include <linux/platform_data/cros_ec_proto.h>
+#include <linux/platform_device.h>
+#include <linux/usb/typec.h>
+
+#define DRV_NAME "cros-ec-typec"
+
+/* Platform-specific data for the Chrome OS EC Type C controller. */
+struct cros_typec_data {
+ struct device *dev;
+ struct cros_ec_device *ec;
+ int num_ports;
+ /* Array of ports, indexed by port number. */
+ struct typec_port *ports[EC_USB_PD_MAX_PORTS];
+};
+
+static int cros_typec_parse_port_props(struct typec_capability *cap,
+ struct fwnode_handle *fwnode,
+ struct device *dev)
+{
+ const char *buf;
+ int ret;
+
+ memset(cap, 0, sizeof(*cap));
+ ret = fwnode_property_read_string(fwnode, "power-role", &buf);
+ if (ret) {
+ dev_err(dev, "power-role not found: %d\n", ret);
+ return ret;
+ }
+
+ ret = typec_find_port_power_role(buf);
+ if (ret < 0)
+ return ret;
+ cap->type = ret;
+
+ ret = fwnode_property_read_string(fwnode, "data-role", &buf);
+ if (ret) {
+ dev_err(dev, "data-role not found: %d\n", ret);
+ return ret;
+ }
+
+ ret = typec_find_port_data_role(buf);
+ if (ret < 0)
+ return ret;
+ cap->data = ret;
+
+ ret = fwnode_property_read_string(fwnode, "try-power-role", &buf);
+ if (ret) {
+ dev_err(dev, "try-power-role not found: %d\n", ret);
+ return ret;
+ }
+
+ ret = typec_find_power_role(buf);
+ if (ret < 0)
+ return ret;
+ cap->prefer_role = ret;
+
+ cap->fwnode = fwnode;
+
+ return 0;
+}
+
+static int cros_typec_init_ports(struct cros_typec_data *typec)
+{
+ struct device *dev = typec->dev;
+ struct typec_capability cap;
+ struct fwnode_handle *fwnode;
+ int ret;
+ int i;
+ int nports;
+ u32 port_num;
+
+ nports = device_get_child_node_count(dev);
+ if (nports == 0) {
+ dev_err(dev, "No port entries found.\n");
+ return -ENODEV;
+ }
+
+ device_for_each_child_node(dev, fwnode) {
+ if (fwnode_property_read_u32(fwnode, "port-number",
+ &port_num)) {
+ dev_err(dev, "No port-number for port, skipping.\n");
+ ret = -EINVAL;
+ goto unregister_ports;
+ }
+
+ if (port_num >= typec->num_ports) {
+ dev_err(dev, "Invalid port number.\n");
+ ret = -EINVAL;
+ goto unregister_ports;
+ }
+
+ dev_dbg(dev, "Registering port %d\n", port_num);
+ ret = cros_typec_parse_port_props(&cap, fwnode, dev);
+ if (ret < 0)
+ goto unregister_ports;
+ typec->ports[port_num] = typec_register_port(dev, &cap);
+ if (IS_ERR(typec->ports[port_num])) {
+ dev_err(dev, "Failed to register port %d\n", port_num);
+ ret = PTR_ERR(typec->ports[port_num]);
+ goto unregister_ports;
+ }
+ }
+
+ return 0;
+
+unregister_ports:
+ for (i = 0; i < typec->num_ports; i++)
+ typec_unregister_port(typec->ports[i]);
+ return ret;
+}
+
+static int cros_typec_ec_command(struct cros_typec_data *typec,
+ unsigned int version,
+ unsigned int command,
+ void *outdata,
+ unsigned int outsize,
+ void *indata,
+ unsigned int insize)
+{
+ struct cros_ec_command *msg;
+ int ret;
+
+ msg = kzalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL);
+ if (!msg)
+ return -ENOMEM;
+
+ msg->version = version;
+ msg->command = command;
+ msg->outsize = outsize;
+ msg->insize = insize;
+
+ if (outsize)
+ memcpy(msg->data, outdata, outsize);
+
+ ret = cros_ec_cmd_xfer_status(typec->ec, msg);
+ if (ret >= 0 && insize)
+ memcpy(indata, msg->data, insize);
+
+ kfree(msg);
+ return ret;
+}
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id cros_typec_acpi_id[] = {
+ { "GOOG0014", 0 },
+ {}
+};
+MODULE_DEVICE_TABLE(acpi, cros_typec_acpi_id);
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id cros_typec_of_match[] = {
+ { .compatible = "google,cros-ec-typec", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cros_typec_of_match);
+#endif
+
+static int cros_typec_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct cros_typec_data *typec;
+ struct ec_response_usb_pd_ports resp;
+ int ret;
+
+ typec = devm_kzalloc(dev, sizeof(*typec), GFP_KERNEL);
+ if (!typec)
+ return -ENOMEM;
+ typec->dev = dev;
+ typec->ec = dev_get_drvdata(pdev->dev.parent);
+ platform_set_drvdata(pdev, typec);
+
+ ret = cros_typec_ec_command(typec, 0, EC_CMD_USB_PD_PORTS, NULL, 0,
+ &resp, sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ typec->num_ports = resp.num_ports;
+ if (typec->num_ports > EC_USB_PD_MAX_PORTS) {
+ dev_warn(typec->dev,
+ "Too many ports reported: %d, limiting to max: %d\n",
+ typec->num_ports, EC_USB_PD_MAX_PORTS);
+ typec->num_ports = EC_USB_PD_MAX_PORTS;
+ }
+
+ ret = cros_typec_init_ports(typec);
+ if (!ret)
+ return ret;
+
+ return 0;
+}
+
+static struct platform_driver cros_typec_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .acpi_match_table = ACPI_PTR(cros_typec_acpi_id),
+ .of_match_table = of_match_ptr(cros_typec_of_match),
+ },
+ .probe = cros_typec_probe,
+};
+
+module_platform_driver(cros_typec_driver);
+
+MODULE_AUTHOR("Prashant Malani <pmalani@chromium.org>");
+MODULE_DESCRIPTION("Chrome OS EC Type C control");
+MODULE_LICENSE("GPL");
--
2.25.0.341.g760bfbb309-goog
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/4] platform/chrome: Add Type C connector class driver
2020-02-07 20:37 ` [PATCH v2 2/4] platform/chrome: Add Type C connector class driver Prashant Malani
@ 2020-02-11 11:26 ` Enric Balletbo i Serra
2020-02-12 16:53 ` Heikki Krogerus
1 sibling, 0 replies; 12+ messages in thread
From: Enric Balletbo i Serra @ 2020-02-11 11:26 UTC (permalink / raw)
To: Prashant Malani, linux-kernel
Cc: heikki.krogerus, bleung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland, Rob Herring
Hi Prashant, Heikki
On 7/2/20 21:37, Prashant Malani wrote:
> Add a driver to implement the Type C connector class for Chrome OS
> devices with ECs (Embedded Controllers).
>
> The driver relies on firmware device specifications for various port
> attributes. On ACPI platforms, this is specified using the logical
> device with HID GOOG0014. On DT platforms, this is specified using the
> DT node with compatible string "google,cros-ec-typec".
>
> This patch reads the device FW node and uses the port attributes to
> register the typec ports with the Type C connector class framework, but
> doesn't do much else.
>
> Subsequent patches will add more functionality to the driver, including
> obtaining current port information (polarity, vconn role, current power
> role etc.) after querying the EC.
>
> Signed-off-by: Prashant Malani <pmalani@chromium.org>
> ---
Would be good a review from Heikki if possible.
>
> Changes in v2:
> - Updated Kconfig to default to MFD_CROS_EC_DEV.
> - Fixed code comments.
> - Moved get_num_ports() code into probe().
> - Added module author.
>
> drivers/platform/chrome/Kconfig | 11 ++
> drivers/platform/chrome/Makefile | 1 +
> drivers/platform/chrome/cros_ec_typec.c | 218 ++++++++++++++++++++++++
> 3 files changed, 230 insertions(+)
> create mode 100644 drivers/platform/chrome/cros_ec_typec.c
>
> diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
> index 5f57282a28da00..2320a4f0d93019 100644
> --- a/drivers/platform/chrome/Kconfig
> +++ b/drivers/platform/chrome/Kconfig
> @@ -214,6 +214,17 @@ config CROS_EC_SYSFS
> To compile this driver as a module, choose M here: the
> module will be called cros_ec_sysfs.
>
> +config CROS_EC_TYPEC
> + tristate "ChromeOS EC Type-C Connector Control"
> + depends on MFD_CROS_EC_DEV && TYPEC
> + default MFD_CROS_EC_DEV
> + help
> + If you say Y here, you get support for accessing Type C connector
> + information from the Chrome OS EC.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called cros_ec_typec.
> +
> config CROS_USBPD_LOGGER
> tristate "Logging driver for USB PD charger"
> depends on CHARGER_CROS_USBPD
> diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
> index aacd5920d8a180..caf2a9cdb5e6d1 100644
> --- a/drivers/platform/chrome/Makefile
> +++ b/drivers/platform/chrome/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_ISHTP) += cros_ec_ishtp.o
> obj-$(CONFIG_CROS_EC_RPMSG) += cros_ec_rpmsg.o
> obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
> cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o
> +obj-$(CONFIG_CROS_EC_TYPEC) += cros_ec_typec.o
> obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
> obj-$(CONFIG_CROS_EC_PROTO) += cros_ec_proto.o cros_ec_trace.o
> obj-$(CONFIG_CROS_KBD_LED_BACKLIGHT) += cros_kbd_led_backlight.o
> diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> new file mode 100644
> index 00000000000000..8374ccfe784f3b
> --- /dev/null
> +++ b/drivers/platform/chrome/cros_ec_typec.c
> @@ -0,0 +1,218 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2020 Google LLC
> + *
> + * This driver provides the ability to view and manage Type C ports through the
> + * Chrome OS EC.
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_data/cros_ec_commands.h>
> +#include <linux/platform_data/cros_ec_proto.h>
> +#include <linux/platform_device.h>
> +#include <linux/usb/typec.h>
> +
> +#define DRV_NAME "cros-ec-typec"
> +
> +/* Platform-specific data for the Chrome OS EC Type C controller. */
> +struct cros_typec_data {
> + struct device *dev;
> + struct cros_ec_device *ec;
> + int num_ports;
> + /* Array of ports, indexed by port number. */
> + struct typec_port *ports[EC_USB_PD_MAX_PORTS];
> +};
> +
> +static int cros_typec_parse_port_props(struct typec_capability *cap,
> + struct fwnode_handle *fwnode,
> + struct device *dev)
> +{
> + const char *buf;
> + int ret;
> +
> + memset(cap, 0, sizeof(*cap));
> + ret = fwnode_property_read_string(fwnode, "power-role", &buf);
> + if (ret) {
> + dev_err(dev, "power-role not found: %d\n", ret);
> + return ret;
> + }
> +
> + ret = typec_find_port_power_role(buf);
> + if (ret < 0)
> + return ret;
> + cap->type = ret;
> +
> + ret = fwnode_property_read_string(fwnode, "data-role", &buf);
> + if (ret) {
> + dev_err(dev, "data-role not found: %d\n", ret);
> + return ret;
> + }
> +
> + ret = typec_find_port_data_role(buf);
> + if (ret < 0)
> + return ret;
> + cap->data = ret;
> +
> + ret = fwnode_property_read_string(fwnode, "try-power-role", &buf);
> + if (ret) {
> + dev_err(dev, "try-power-role not found: %d\n", ret);
> + return ret;
> + }
> +
> + ret = typec_find_power_role(buf);
> + if (ret < 0)
> + return ret;
> + cap->prefer_role = ret;
> +
> + cap->fwnode = fwnode;
> +
> + return 0;
> +}
> +
> +static int cros_typec_init_ports(struct cros_typec_data *typec)
> +{
> + struct device *dev = typec->dev;
> + struct typec_capability cap;
> + struct fwnode_handle *fwnode;
> + int ret;
> + int i;
> + int nports;
> + u32 port_num;
> +
> + nports = device_get_child_node_count(dev);
> + if (nports == 0) {
> + dev_err(dev, "No port entries found.\n");
> + return -ENODEV;
> + }
> +
> + device_for_each_child_node(dev, fwnode) {
> + if (fwnode_property_read_u32(fwnode, "port-number",
> + &port_num)) {
> + dev_err(dev, "No port-number for port, skipping.\n");
> + ret = -EINVAL;
> + goto unregister_ports;
> + }
> +
> + if (port_num >= typec->num_ports) {
> + dev_err(dev, "Invalid port number.\n");
> + ret = -EINVAL;
> + goto unregister_ports;
> + }
> +
> + dev_dbg(dev, "Registering port %d\n", port_num);
> + ret = cros_typec_parse_port_props(&cap, fwnode, dev);
> + if (ret < 0)
> + goto unregister_ports;
> + typec->ports[port_num] = typec_register_port(dev, &cap);
> + if (IS_ERR(typec->ports[port_num])) {
> + dev_err(dev, "Failed to register port %d\n", port_num);
> + ret = PTR_ERR(typec->ports[port_num]);
> + goto unregister_ports;
> + }
> + }
> +
> + return 0;
> +
> +unregister_ports:
> + for (i = 0; i < typec->num_ports; i++)
> + typec_unregister_port(typec->ports[i]);
> + return ret;
> +}
> +
> +static int cros_typec_ec_command(struct cros_typec_data *typec,
> + unsigned int version,
> + unsigned int command,
> + void *outdata,
> + unsigned int outsize,
> + void *indata,
> + unsigned int insize)
> +{
> + struct cros_ec_command *msg;
> + int ret;
> +
> + msg = kzalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL);
> + if (!msg)
> + return -ENOMEM;
> +
> + msg->version = version;
> + msg->command = command;
> + msg->outsize = outsize;
> + msg->insize = insize;
> +
> + if (outsize)
> + memcpy(msg->data, outdata, outsize);
> +
> + ret = cros_ec_cmd_xfer_status(typec->ec, msg);
> + if (ret >= 0 && insize)
> + memcpy(indata, msg->data, insize);
> +
> + kfree(msg);
> + return ret;
> +}
> +
> +#ifdef CONFIG_ACPI
> +static const struct acpi_device_id cros_typec_acpi_id[] = {
> + { "GOOG0014", 0 },
> + {}
> +};
> +MODULE_DEVICE_TABLE(acpi, cros_typec_acpi_id);
> +#endif
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id cros_typec_of_match[] = {
> + { .compatible = "google,cros-ec-typec", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, cros_typec_of_match);
> +#endif
> +
> +static int cros_typec_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cros_typec_data *typec;
> + struct ec_response_usb_pd_ports resp;
> + int ret;
> +
> + typec = devm_kzalloc(dev, sizeof(*typec), GFP_KERNEL);
> + if (!typec)
> + return -ENOMEM;
> + typec->dev = dev;
> + typec->ec = dev_get_drvdata(pdev->dev.parent);
> + platform_set_drvdata(pdev, typec);
> +
> + ret = cros_typec_ec_command(typec, 0, EC_CMD_USB_PD_PORTS, NULL, 0,
> + &resp, sizeof(resp));
> + if (ret < 0)
> + return ret;
> +
> + typec->num_ports = resp.num_ports;
> + if (typec->num_ports > EC_USB_PD_MAX_PORTS) {
> + dev_warn(typec->dev,
> + "Too many ports reported: %d, limiting to max: %d\n",
> + typec->num_ports, EC_USB_PD_MAX_PORTS);
> + typec->num_ports = EC_USB_PD_MAX_PORTS;
> + }
> +
> + ret = cros_typec_init_ports(typec);
> + if (!ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static struct platform_driver cros_typec_driver = {
> + .driver = {
> + .name = DRV_NAME,
> + .acpi_match_table = ACPI_PTR(cros_typec_acpi_id),
> + .of_match_table = of_match_ptr(cros_typec_of_match),
> + },
> + .probe = cros_typec_probe,
> +};
> +
> +module_platform_driver(cros_typec_driver);
> +
> +MODULE_AUTHOR("Prashant Malani <pmalani@chromium.org>");
> +MODULE_DESCRIPTION("Chrome OS EC Type C control");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/4] platform/chrome: Add Type C connector class driver
2020-02-07 20:37 ` [PATCH v2 2/4] platform/chrome: Add Type C connector class driver Prashant Malani
2020-02-11 11:26 ` Enric Balletbo i Serra
@ 2020-02-12 16:53 ` Heikki Krogerus
1 sibling, 0 replies; 12+ messages in thread
From: Heikki Krogerus @ 2020-02-12 16:53 UTC (permalink / raw)
To: Prashant Malani
Cc: linux-kernel, heikki.krogerus, enric.balletbo, bleung,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Guenter Roeck, Mark Rutland, Rob Herring
On Fri, Feb 07, 2020 at 12:37:46PM -0800, Prashant Malani wrote:
> Add a driver to implement the Type C connector class for Chrome OS
> devices with ECs (Embedded Controllers).
>
> The driver relies on firmware device specifications for various port
> attributes. On ACPI platforms, this is specified using the logical
> device with HID GOOG0014. On DT platforms, this is specified using the
> DT node with compatible string "google,cros-ec-typec".
>
> This patch reads the device FW node and uses the port attributes to
> register the typec ports with the Type C connector class framework, but
> doesn't do much else.
>
> Subsequent patches will add more functionality to the driver, including
> obtaining current port information (polarity, vconn role, current power
> role etc.) after querying the EC.
>
> Signed-off-by: Prashant Malani <pmalani@chromium.org>
Besides the few minor nitpicks below, looks OK to me.
> ---
>
> Changes in v2:
> - Updated Kconfig to default to MFD_CROS_EC_DEV.
> - Fixed code comments.
> - Moved get_num_ports() code into probe().
> - Added module author.
>
> drivers/platform/chrome/Kconfig | 11 ++
> drivers/platform/chrome/Makefile | 1 +
> drivers/platform/chrome/cros_ec_typec.c | 218 ++++++++++++++++++++++++
> 3 files changed, 230 insertions(+)
> create mode 100644 drivers/platform/chrome/cros_ec_typec.c
>
> diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
> index 5f57282a28da00..2320a4f0d93019 100644
> --- a/drivers/platform/chrome/Kconfig
> +++ b/drivers/platform/chrome/Kconfig
> @@ -214,6 +214,17 @@ config CROS_EC_SYSFS
> To compile this driver as a module, choose M here: the
> module will be called cros_ec_sysfs.
>
> +config CROS_EC_TYPEC
> + tristate "ChromeOS EC Type-C Connector Control"
> + depends on MFD_CROS_EC_DEV && TYPEC
> + default MFD_CROS_EC_DEV
> + help
> + If you say Y here, you get support for accessing Type C connector
> + information from the Chrome OS EC.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called cros_ec_typec.
> +
> config CROS_USBPD_LOGGER
> tristate "Logging driver for USB PD charger"
> depends on CHARGER_CROS_USBPD
> diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
> index aacd5920d8a180..caf2a9cdb5e6d1 100644
> --- a/drivers/platform/chrome/Makefile
> +++ b/drivers/platform/chrome/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_ISHTP) += cros_ec_ishtp.o
> obj-$(CONFIG_CROS_EC_RPMSG) += cros_ec_rpmsg.o
> obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
> cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o
> +obj-$(CONFIG_CROS_EC_TYPEC) += cros_ec_typec.o
> obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
> obj-$(CONFIG_CROS_EC_PROTO) += cros_ec_proto.o cros_ec_trace.o
> obj-$(CONFIG_CROS_KBD_LED_BACKLIGHT) += cros_kbd_led_backlight.o
> diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> new file mode 100644
> index 00000000000000..8374ccfe784f3b
> --- /dev/null
> +++ b/drivers/platform/chrome/cros_ec_typec.c
> @@ -0,0 +1,218 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2020 Google LLC
> + *
> + * This driver provides the ability to view and manage Type C ports through the
> + * Chrome OS EC.
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_data/cros_ec_commands.h>
> +#include <linux/platform_data/cros_ec_proto.h>
> +#include <linux/platform_device.h>
> +#include <linux/usb/typec.h>
> +
> +#define DRV_NAME "cros-ec-typec"
> +
> +/* Platform-specific data for the Chrome OS EC Type C controller. */
> +struct cros_typec_data {
> + struct device *dev;
> + struct cros_ec_device *ec;
> + int num_ports;
> + /* Array of ports, indexed by port number. */
> + struct typec_port *ports[EC_USB_PD_MAX_PORTS];
> +};
> +
> +static int cros_typec_parse_port_props(struct typec_capability *cap,
> + struct fwnode_handle *fwnode,
> + struct device *dev)
> +{
> + const char *buf;
> + int ret;
> +
> + memset(cap, 0, sizeof(*cap));
> + ret = fwnode_property_read_string(fwnode, "power-role", &buf);
> + if (ret) {
> + dev_err(dev, "power-role not found: %d\n", ret);
> + return ret;
> + }
> +
> + ret = typec_find_port_power_role(buf);
> + if (ret < 0)
> + return ret;
> + cap->type = ret;
> +
> + ret = fwnode_property_read_string(fwnode, "data-role", &buf);
> + if (ret) {
> + dev_err(dev, "data-role not found: %d\n", ret);
> + return ret;
> + }
> +
> + ret = typec_find_port_data_role(buf);
> + if (ret < 0)
> + return ret;
> + cap->data = ret;
> +
> + ret = fwnode_property_read_string(fwnode, "try-power-role", &buf);
> + if (ret) {
> + dev_err(dev, "try-power-role not found: %d\n", ret);
> + return ret;
> + }
> +
> + ret = typec_find_power_role(buf);
> + if (ret < 0)
> + return ret;
> + cap->prefer_role = ret;
> +
> + cap->fwnode = fwnode;
> +
> + return 0;
> +}
> +
> +static int cros_typec_init_ports(struct cros_typec_data *typec)
> +{
> + struct device *dev = typec->dev;
> + struct typec_capability cap;
> + struct fwnode_handle *fwnode;
> + int ret;
> + int i;
> + int nports;
> + u32 port_num;
> +
> + nports = device_get_child_node_count(dev);
> + if (nports == 0) {
> + dev_err(dev, "No port entries found.\n");
> + return -ENODEV;
> + }
> +
> + device_for_each_child_node(dev, fwnode) {
> + if (fwnode_property_read_u32(fwnode, "port-number",
> + &port_num)) {
> + dev_err(dev, "No port-number for port, skipping.\n");
> + ret = -EINVAL;
> + goto unregister_ports;
> + }
> +
> + if (port_num >= typec->num_ports) {
> + dev_err(dev, "Invalid port number.\n");
> + ret = -EINVAL;
> + goto unregister_ports;
> + }
> +
> + dev_dbg(dev, "Registering port %d\n", port_num);
Empty line?
> + ret = cros_typec_parse_port_props(&cap, fwnode, dev);
> + if (ret < 0)
> + goto unregister_ports;
ditto
> + typec->ports[port_num] = typec_register_port(dev, &cap);
> + if (IS_ERR(typec->ports[port_num])) {
> + dev_err(dev, "Failed to register port %d\n", port_num);
> + ret = PTR_ERR(typec->ports[port_num]);
> + goto unregister_ports;
> + }
> + }
> +
> + return 0;
> +
> +unregister_ports:
> + for (i = 0; i < typec->num_ports; i++)
> + typec_unregister_port(typec->ports[i]);
> + return ret;
> +}
> +
> +static int cros_typec_ec_command(struct cros_typec_data *typec,
> + unsigned int version,
> + unsigned int command,
> + void *outdata,
> + unsigned int outsize,
> + void *indata,
> + unsigned int insize)
> +{
> + struct cros_ec_command *msg;
> + int ret;
> +
> + msg = kzalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL);
> + if (!msg)
> + return -ENOMEM;
> +
> + msg->version = version;
> + msg->command = command;
> + msg->outsize = outsize;
> + msg->insize = insize;
> +
> + if (outsize)
> + memcpy(msg->data, outdata, outsize);
> +
> + ret = cros_ec_cmd_xfer_status(typec->ec, msg);
> + if (ret >= 0 && insize)
> + memcpy(indata, msg->data, insize);
> +
> + kfree(msg);
> + return ret;
> +}
> +
> +#ifdef CONFIG_ACPI
> +static const struct acpi_device_id cros_typec_acpi_id[] = {
> + { "GOOG0014", 0 },
> + {}
> +};
> +MODULE_DEVICE_TABLE(acpi, cros_typec_acpi_id);
> +#endif
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id cros_typec_of_match[] = {
> + { .compatible = "google,cros-ec-typec", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, cros_typec_of_match);
> +#endif
> +
> +static int cros_typec_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cros_typec_data *typec;
> + struct ec_response_usb_pd_ports resp;
> + int ret;
> +
> + typec = devm_kzalloc(dev, sizeof(*typec), GFP_KERNEL);
> + if (!typec)
> + return -ENOMEM;
Empty line here.
> + typec->dev = dev;
> + typec->ec = dev_get_drvdata(pdev->dev.parent);
> + platform_set_drvdata(pdev, typec);
> +
> + ret = cros_typec_ec_command(typec, 0, EC_CMD_USB_PD_PORTS, NULL, 0,
> + &resp, sizeof(resp));
> + if (ret < 0)
> + return ret;
> +
> + typec->num_ports = resp.num_ports;
> + if (typec->num_ports > EC_USB_PD_MAX_PORTS) {
> + dev_warn(typec->dev,
> + "Too many ports reported: %d, limiting to max: %d\n",
> + typec->num_ports, EC_USB_PD_MAX_PORTS);
> + typec->num_ports = EC_USB_PD_MAX_PORTS;
> + }
> +
> + ret = cros_typec_init_ports(typec);
> + if (!ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static struct platform_driver cros_typec_driver = {
> + .driver = {
> + .name = DRV_NAME,
> + .acpi_match_table = ACPI_PTR(cros_typec_acpi_id),
> + .of_match_table = of_match_ptr(cros_typec_of_match),
> + },
> + .probe = cros_typec_probe,
> +};
> +
> +module_platform_driver(cros_typec_driver);
> +
> +MODULE_AUTHOR("Prashant Malani <pmalani@chromium.org>");
> +MODULE_DESCRIPTION("Chrome OS EC Type C control");
> +MODULE_LICENSE("GPL");
> --
> 2.25.0.341.g760bfbb309-goog
--
heikki
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/4] platform/chrome: typec: Get PD_CONTROL cmd version
2020-02-07 20:37 [PATCH v2 0/4] platform/chrome: Add Type C connector class driver Prashant Malani
2020-02-07 20:37 ` [PATCH v2 1/4] dt-bindings: Add cros-ec Type C port driver Prashant Malani
2020-02-07 20:37 ` [PATCH v2 2/4] platform/chrome: Add Type C connector class driver Prashant Malani
@ 2020-02-07 20:37 ` Prashant Malani
2020-02-11 10:52 ` Enric Balletbo i Serra
2020-02-07 20:37 ` [PATCH v2 4/4] platform/chrome: typec: Update port info from EC Prashant Malani
3 siblings, 1 reply; 12+ messages in thread
From: Prashant Malani @ 2020-02-07 20:37 UTC (permalink / raw)
To: linux-kernel
Cc: heikki.krogerus, enric.balletbo, bleung, Prashant Malani, Guenter Roeck
Query the EC to determine the version number of the PD_CONTROL
command which is supported by the EC. Also store this value in the Type
C data struct since it will be used to determine how to parse the
response to queries for port information from the EC.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
---
Changes in v2:
- No changes.
drivers/platform/chrome/cros_ec_typec.c | 34 ++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index 8374ccfe784f3b..df01ce86c7146c 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -21,6 +21,7 @@ struct cros_typec_data {
struct device *dev;
struct cros_ec_device *ec;
int num_ports;
+ unsigned int cmd_ver;
/* Array of ports, indexed by port number. */
struct typec_port *ports[EC_USB_PD_MAX_PORTS];
};
@@ -152,6 +153,31 @@ static int cros_typec_ec_command(struct cros_typec_data *typec,
return ret;
}
+static int cros_typec_get_cmd_version(struct cros_typec_data *typec)
+{
+ struct ec_params_get_cmd_versions_v1 req_v1;
+ struct ec_response_get_cmd_versions resp;
+ int ret;
+
+ /* We're interested in the PD control command version. */
+ req_v1.cmd = EC_CMD_USB_PD_CONTROL;
+ ret = cros_typec_ec_command(typec, 1, EC_CMD_GET_CMD_VERSIONS,
+ &req_v1, sizeof(req_v1), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ if (resp.version_mask & EC_VER_MASK(1))
+ typec->cmd_ver = 1;
+ else
+ typec->cmd_ver = 0;
+
+ dev_dbg(typec->dev, "PD Control has version mask 0x%hhx\n",
+ typec->cmd_ver);
+
+ return 0;
+}
+
#ifdef CONFIG_ACPI
static const struct acpi_device_id cros_typec_acpi_id[] = {
{ "GOOG0014", 0 },
@@ -182,6 +208,12 @@ static int cros_typec_probe(struct platform_device *pdev)
typec->ec = dev_get_drvdata(pdev->dev.parent);
platform_set_drvdata(pdev, typec);
+ ret = cros_typec_get_cmd_version(typec);
+ if (ret < 0) {
+ dev_err(dev, "failed to get PD command version info\n");
+ return ret;
+ }
+
ret = cros_typec_ec_command(typec, 0, EC_CMD_USB_PD_PORTS, NULL, 0,
&resp, sizeof(resp));
if (ret < 0)
@@ -196,7 +228,7 @@ static int cros_typec_probe(struct platform_device *pdev)
}
ret = cros_typec_init_ports(typec);
- if (!ret)
+ if (ret < 0)
return ret;
return 0;
--
2.25.0.341.g760bfbb309-goog
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/4] platform/chrome: typec: Get PD_CONTROL cmd version
2020-02-07 20:37 ` [PATCH v2 3/4] platform/chrome: typec: Get PD_CONTROL cmd version Prashant Malani
@ 2020-02-11 10:52 ` Enric Balletbo i Serra
0 siblings, 0 replies; 12+ messages in thread
From: Enric Balletbo i Serra @ 2020-02-11 10:52 UTC (permalink / raw)
To: Prashant Malani, linux-kernel; +Cc: heikki.krogerus, bleung, Guenter Roeck
Hi Prashant,
On 7/2/20 21:37, Prashant Malani wrote:
> Query the EC to determine the version number of the PD_CONTROL
> command which is supported by the EC. Also store this value in the Type
> C data struct since it will be used to determine how to parse the
> response to queries for port information from the EC.
>
> Signed-off-by: Prashant Malani <pmalani@chromium.org>
> ---
>
> Changes in v2:
> - No changes.
>
> drivers/platform/chrome/cros_ec_typec.c | 34 ++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> index 8374ccfe784f3b..df01ce86c7146c 100644
> --- a/drivers/platform/chrome/cros_ec_typec.c
> +++ b/drivers/platform/chrome/cros_ec_typec.c
> @@ -21,6 +21,7 @@ struct cros_typec_data {
> struct device *dev;
> struct cros_ec_device *ec;
> int num_ports;
> + unsigned int cmd_ver;
> /* Array of ports, indexed by port number. */
> struct typec_port *ports[EC_USB_PD_MAX_PORTS];
> };
> @@ -152,6 +153,31 @@ static int cros_typec_ec_command(struct cros_typec_data *typec,
> return ret;
> }
>
> +static int cros_typec_get_cmd_version(struct cros_typec_data *typec)
> +{
> + struct ec_params_get_cmd_versions_v1 req_v1;
> + struct ec_response_get_cmd_versions resp;
> + int ret;
> +
> + /* We're interested in the PD control command version. */
> + req_v1.cmd = EC_CMD_USB_PD_CONTROL;
> + ret = cros_typec_ec_command(typec, 1, EC_CMD_GET_CMD_VERSIONS,
> + &req_v1, sizeof(req_v1), &resp,
> + sizeof(resp));
> + if (ret < 0)
> + return ret;
> +
> + if (resp.version_mask & EC_VER_MASK(1))
> + typec->cmd_ver = 1;
> + else
> + typec->cmd_ver = 0;
> +
> + dev_dbg(typec->dev, "PD Control has version mask 0x%hhx\n",
> + typec->cmd_ver);
> +
> + return 0;
> +}
> +
> #ifdef CONFIG_ACPI
> static const struct acpi_device_id cros_typec_acpi_id[] = {
> { "GOOG0014", 0 },
> @@ -182,6 +208,12 @@ static int cros_typec_probe(struct platform_device *pdev)
> typec->ec = dev_get_drvdata(pdev->dev.parent);
> platform_set_drvdata(pdev, typec);
>
> + ret = cros_typec_get_cmd_version(typec);
> + if (ret < 0) {
> + dev_err(dev, "failed to get PD command version info\n");
> + return ret;
> + }
> +
> ret = cros_typec_ec_command(typec, 0, EC_CMD_USB_PD_PORTS, NULL, 0,
> &resp, sizeof(resp));
> if (ret < 0)
> @@ -196,7 +228,7 @@ static int cros_typec_probe(struct platform_device *pdev)
> }
>
> ret = cros_typec_init_ports(typec);
> - if (!ret)
> + if (ret < 0)
Looks like this change should be in patch 2/4?
> return ret;
>
> return 0;
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/4] platform/chrome: typec: Update port info from EC
2020-02-07 20:37 [PATCH v2 0/4] platform/chrome: Add Type C connector class driver Prashant Malani
` (2 preceding siblings ...)
2020-02-07 20:37 ` [PATCH v2 3/4] platform/chrome: typec: Get PD_CONTROL cmd version Prashant Malani
@ 2020-02-07 20:37 ` Prashant Malani
3 siblings, 0 replies; 12+ messages in thread
From: Prashant Malani @ 2020-02-07 20:37 UTC (permalink / raw)
To: linux-kernel
Cc: heikki.krogerus, enric.balletbo, bleung, Prashant Malani,
Jon Flatley, Guenter Roeck
After registering the ports at probe, get the current port information
from EC and update the Type C connector class ports accordingly.
Co-developed-by: Jon Flatley <jflat@chromium.org>
Signed-off-by: Prashant Malani <pmalani@chromium.org>
---
Changes in v2:
- No changes.
drivers/platform/chrome/cros_ec_typec.c | 89 ++++++++++++++++++++++++-
1 file changed, 88 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index df01ce86c7146c..4cdbd85966ee02 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -153,6 +153,81 @@ static int cros_typec_ec_command(struct cros_typec_data *typec,
return ret;
}
+static void cros_typec_set_port_params_v0(struct cros_typec_data *typec,
+ int port_num, struct ec_response_usb_pd_control *resp)
+{
+ struct typec_port *port = typec->ports[port_num];
+ enum typec_orientation polarity;
+
+ if (!resp->enabled)
+ polarity = TYPEC_ORIENTATION_NONE;
+ else if (!resp->polarity)
+ polarity = TYPEC_ORIENTATION_NORMAL;
+ else
+ polarity = TYPEC_ORIENTATION_REVERSE;
+
+ typec_set_pwr_role(port, resp->role ? TYPEC_SOURCE : TYPEC_SINK);
+ typec_set_orientation(port, polarity);
+}
+
+static void cros_typec_set_port_params_v1(struct cros_typec_data *typec,
+ int port_num, struct ec_response_usb_pd_control_v1 *resp)
+{
+ struct typec_port *port = typec->ports[port_num];
+ enum typec_orientation polarity;
+
+ if (!(resp->enabled & PD_CTRL_RESP_ENABLED_CONNECTED))
+ polarity = TYPEC_ORIENTATION_NONE;
+ else if (!resp->polarity)
+ polarity = TYPEC_ORIENTATION_NORMAL;
+ else
+ polarity = TYPEC_ORIENTATION_REVERSE;
+ typec_set_orientation(port, polarity);
+ typec_set_data_role(port, resp->role & PD_CTRL_RESP_ROLE_DATA ?
+ TYPEC_HOST : TYPEC_DEVICE);
+ typec_set_pwr_role(port, resp->role & PD_CTRL_RESP_ROLE_POWER ?
+ TYPEC_SOURCE : TYPEC_SINK);
+ typec_set_vconn_role(port, resp->role & PD_CTRL_RESP_ROLE_VCONN ?
+ TYPEC_SOURCE : TYPEC_SINK);
+}
+
+static int cros_typec_port_update(struct cros_typec_data *typec, int port_num)
+{
+ struct ec_params_usb_pd_control req;
+ struct ec_response_usb_pd_control_v1 resp;
+ int ret;
+
+ if (port_num < 0 || port_num >= typec->num_ports) {
+ dev_err(typec->dev, "cannot get status for invalid port %d\n",
+ port_num);
+ return -EINVAL;
+ }
+
+ req.port = port_num;
+ req.role = USB_PD_CTRL_ROLE_NO_CHANGE;
+ req.mux = USB_PD_CTRL_MUX_NO_CHANGE;
+ req.swap = USB_PD_CTRL_SWAP_NONE;
+
+ ret = cros_typec_ec_command(typec, typec->cmd_ver,
+ EC_CMD_USB_PD_CONTROL, &req, sizeof(req),
+ &resp, sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(typec->dev, "Enabled %d: 0x%hhx\n", port_num, resp.enabled);
+ dev_dbg(typec->dev, "Role %d: 0x%hhx\n", port_num, resp.role);
+ dev_dbg(typec->dev, "Polarity %d: 0x%hhx\n", port_num, resp.polarity);
+ dev_dbg(typec->dev, "State %d: %s\n", port_num, resp.state);
+
+ if (typec->cmd_ver == 1)
+ cros_typec_set_port_params_v1(typec, port_num, &resp);
+ else
+ cros_typec_set_port_params_v0(typec, port_num,
+ (struct ec_response_usb_pd_control *) &resp);
+
+ return 0;
+}
+
static int cros_typec_get_cmd_version(struct cros_typec_data *typec)
{
struct ec_params_get_cmd_versions_v1 req_v1;
@@ -199,7 +274,7 @@ static int cros_typec_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct cros_typec_data *typec;
struct ec_response_usb_pd_ports resp;
- int ret;
+ int ret, i;
typec = devm_kzalloc(dev, sizeof(*typec), GFP_KERNEL);
if (!typec)
@@ -231,7 +306,19 @@ static int cros_typec_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
+ for (i = 0; i < typec->num_ports; i++) {
+ ret = cros_typec_port_update(typec, i);
+ if (ret < 0)
+ goto unregister_ports;
+ }
+
return 0;
+
+unregister_ports:
+ for (i = 0; i < typec->num_ports; i++)
+ if (typec->ports[i])
+ typec_unregister_port(typec->ports[i]);
+ return ret;
}
static struct platform_driver cros_typec_driver = {
--
2.25.0.341.g760bfbb309-goog
^ permalink raw reply related [flat|nested] 12+ messages in thread