From: Marc Zyngier <maz@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<palmer@dabbelt.com>,
"Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
<aou@eecs.berkeley.edu>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <bmeng.cn@gmail.com>,
<atish.patra@wdc.com>, Sagar Kadam <sagar.kadam@sifive.com>,
<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Sachin Ghadi <sachin.ghadi@sifive.com>
Subject: Re: [PATCH 1/4] irqchip: sifive: Support hierarchy irq domain
Date: Tue, 12 Nov 2019 13:52:09 +0109 [thread overview]
Message-ID: <ad0a3b419a3f5c3475d5fafcc2a037fb@www.loen.fr> (raw)
In-Reply-To: <1573560684-48104-2-git-send-email-yash.shah@sifive.com>
On 2019-11-12 13:21, Yash Shah wrote:
> Add support for hierarchy irq domains. This is needed as
> pre-requisite for
> gpio-sifive driver.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> drivers/irqchip/Kconfig | 1 +
> drivers/irqchip/irq-sifive-plic.c | 41
> +++++++++++++++++++++++++++++++++++----
> 2 files changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index ccbb897..a398552 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -488,6 +488,7 @@ endmenu
> config SIFIVE_PLIC
> bool "SiFive Platform-Level Interrupt Controller"
> depends on RISCV
> + select IRQ_DOMAIN_HIERARCHY
> help
> This enables support for the PLIC chip found in SiFive (and
> potentially other) RISC-V systems. The PLIC controls devices
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c
> index 7d0a12f..2fa1c84 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -154,15 +154,48 @@ static struct irq_chip plic_chip = {
> static int plic_irqdomain_map(struct irq_domain *d, unsigned int
> irq,
> irq_hw_number_t hwirq)
> {
> - irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq);
> - irq_set_chip_data(irq, NULL);
> + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
> + handle_fasteoi_irq, NULL, NULL);
> irq_set_noprobe(irq);
> return 0;
> }
>
> +static int plic_irq_domain_translate(struct irq_domain *d,
> + struct irq_fwspec *fwspec,
> + unsigned long *hwirq, unsigned int *type)
> +{
> + if (WARN_ON(fwspec->param_count < 1))
> + return -EINVAL;
> + *hwirq = fwspec->param[0];
> + *type = IRQ_TYPE_NONE;
> + return 0;
> +}
This is actually what should be called irq_domain_translate_onecell().
Consider implementing that instead, and using it in this driver. I'm
pretty sure other drivers could use it (I spotted irq-nvic.c).
> +
> +static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned
> int virq,
> + unsigned int nr_irqs, void *arg)
> +{
> + int i, ret;
> + irq_hw_number_t hwirq;
> + unsigned int type = IRQ_TYPE_NONE;
> + struct irq_fwspec *fwspec = arg;
> +
> + ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < nr_irqs; i++) {
> + ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static const struct irq_domain_ops plic_irqdomain_ops = {
> - .map = plic_irqdomain_map,
> - .xlate = irq_domain_xlate_onecell,
> + .translate = plic_irq_domain_translate,
> + .alloc = plic_irq_domain_alloc,
> + .free = irq_domain_free_irqs_top,
> };
>
> static struct irq_domain *plic_irqdomain;
Otherwise, looks OK.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2019-11-12 12:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-12 12:11 [PATCH 0/4] GPIO & Hierarchy IRQ support for HiFive Unleashed Yash Shah
2019-11-12 12:11 ` [PATCH 1/4] irqchip: sifive: Support hierarchy irq domain Yash Shah
2019-11-12 12:43 ` Marc Zyngier [this message]
2019-11-18 7:14 ` Yash Shah
2019-11-12 12:12 ` [PATCH 2/4] gpio: sifive: Add DT documentation for SiFive GPIO Yash Shah
2019-11-18 16:53 ` Rob Herring
2019-11-12 12:12 ` [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs Yash Shah
2019-11-12 12:58 ` Marc Zyngier
2019-11-18 7:50 ` Yash Shah
2019-11-13 13:10 ` Bartosz Golaszewski
2019-11-18 10:03 ` Yash Shah
2019-11-18 10:15 ` Bartosz Golaszewski
2019-11-19 15:02 ` Linus Walleij
2019-11-19 16:41 ` Bartosz Golaszewski
2019-11-22 12:28 ` Linus Walleij
2019-11-22 12:39 ` Bartosz Golaszewski
2019-11-25 4:54 ` Yash Shah
2019-11-12 12:12 ` [PATCH 4/4] riscv: dts: Add DT support for SiFive FU540 GPIO driver Yash Shah
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