From: Martin Schiller <ms@dev.tdt.de>
To: Michael Walle <michael@walle.cc>
Cc: tharvey@gateworks.com, andrew@lunn.ch, davem@davemloft.net,
f.fainelli@gmail.com, hauke@hauke-m.de, hkallweit1@gmail.com,
kuba@kernel.org, linux-kernel@vger.kernel.org,
linux@armlinux.org.uk, martin.blumenstingl@googlemail.com,
netdev@vger.kernel.org
Subject: Re: [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal delay configuration
Date: Fri, 24 Feb 2023 09:48:06 +0100 [thread overview]
Message-ID: <adb55f7dc3b4be01317cf7766e389874@dev.tdt.de> (raw)
In-Reply-To: <df9a0b6e59d27d5898a9021915ca333a@walle.cc>
On 2023-02-24 09:04, Michael Walle wrote:
> Hi Martin,
>
> Am 2023-02-24 07:25, schrieb Martin Schiller:
>> On 2023-02-22 17:04, Michael Walle wrote:
>>> Hi Tim, Hi Martin,
>>>
>>>> I've got some boards with the GPY111 phy on them and I'm finding
>>>> that
>>>> modifying XWAY_MDIO_MIICTRL to change the skew has no effect unless
>>>> I
>>>> do a soft reset (BCMR_RESET) first. I don't see anything in the
>>>> datasheet which specifies this to be the case so I'm interested it
>>>> what you have found. Are you sure adjusting the skews like this
>>>> without a soft (or hard pin based) reset actually works?
>>>
>>> I do have the same PHY and I'm puzzled with the delay settings. Do
>>> you have an EEPROM attached to the PHY? According to my datasheet,
>>> that seems to make a difference. Apparently, only if there is an
>>> EEPROM, you can change the value (the value is then also written to
>>> the EEPROM according the datasheet).
>>> If you don't have one, the values will get overwritten by the
>>> external strappings on a soft reset. Therefore, it seems they cannot
>>> be set. (FWIW there is also a sticky bit, but that doesn't seem to
>>> help in this case).
>>>
>>> -michael
>>
>> Yes, you are right. The datasheet says: "In no-EEPROM mode, writing to
>> this register has no impact on operation of the device".
>>
>> But changing this settings without an EEPROM indeed has an impact.
>>
>> We don't use an EEPROM and without tuning this values some boards are
>> unable to communicate on the ethernet port(s).
>
> Thanks for confirming! Could you share your PHYID1/PHYID2 register and
> firmware version (FWV, 0x1E) contents?
I've 2 PHYs integrated into the VR268 SoC which shows this values:
STD_PHYID1(reg 0x02): 0xd565
STD_PHYID2(reg 0x03): 0xa409
PHY_FWV (reg 0x1E): 0x8435
And then there are 2 external GPY111 with this values:
STD_PHYID1(reg 0x02): 0xd565
STD_PHYID2(reg 0x03): 0xa401
PHY_FWV (reg 0x1E): 0x8435
And one external GPY112 with this values:
STD_PHYID1(reg 0x02): 0xd565
STD_PHYID2(reg 0x03): 0xa401
PHY_FWV (reg 0x1E): 0x8435
>
> In our case, any changes in MIICTRL are lost after a soft reset.
>
>> I varied these values during operation in the uboot and was able to
>> test
>> the limits very nicely.
>
> So I guess, the value you write into MIICTRL are retained on a soft
> reset.
No, the value I write into MIICTRL are not retained on a soft reset.
> I.e.
>
> mii write <phyad> 0x17 0xffff
> mii write <phyad> 0x00 0x8000
> mii read <phyad> 0x17
>
> will still return 0xffff?
In my tests I always set the skew values in register 0x17 first and
then triggered a restart of the ANEG via register 0x0. This then led to
the new values being adopted.
>
>>
>> I wouldn't have introduced this feature if it hasn't got any impact.
>
> Sure, I'm just trying to figure out the differences ;)
>
> Thanks,
> Michael
- Martin
next prev parent reply other threads:[~2023-02-24 8:48 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 8:27 [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal delay configuration Martin Schiller
2021-07-19 20:56 ` Andrew Lunn
2021-07-20 11:50 ` Martin Schiller
2022-01-10 23:12 ` Tim Harvey
2022-01-11 7:44 ` Martin Schiller
2022-01-11 13:34 ` Andrew Lunn
2022-01-11 19:12 ` Tim Harvey
2022-01-12 11:07 ` Martin Schiller
2022-01-12 13:14 ` Andrew Lunn
2022-01-12 18:24 ` Tim Harvey
2022-01-12 13:46 ` Russell King (Oracle)
2022-01-12 18:25 ` Tim Harvey
2022-01-13 6:32 ` Martin Schiller
2022-02-01 20:28 ` Tim Harvey
2022-02-01 20:49 ` Andrew Lunn
2023-02-22 16:04 ` Michael Walle
2023-02-24 6:25 ` Martin Schiller
2023-02-24 8:04 ` Michael Walle
2023-02-24 8:48 ` Martin Schiller [this message]
2023-03-02 15:03 ` Michael Walle
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