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Fri, 29 Apr 2022 15:44:44 -0700 (PDT) Received: from [192.168.2.222] ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id z1-20020a05600c220100b003942a244ed9sm347944wml.30.2022.04.29.15.44.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Apr 2022 15:44:43 -0700 (PDT) Message-ID: Date: Fri, 29 Apr 2022 23:44:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v1 8/8] riscv: dts: microchip: add the sundance polarberry Content-Language: en-US To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daire McNamara , Cyril Jean , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Arnd Bergmann References: <20220429104040.197161-1-conor.dooley@microchip.com> <20220429104040.197161-9-conor.dooley@microchip.com> From: Conor Dooley In-Reply-To: <20220429104040.197161-9-conor.dooley@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/04/2022 11:40, Conor Dooley wrote: > Add a minimal device tree for the PolarFire SoC based Sundance > PolarBerry. > > Signed-off-by: Conor Dooley > --- > arch/riscv/boot/dts/microchip/Makefile | 1 + > .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ > .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ > 3 files changed, 112 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi > create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > index af3a5059b350..39aae7b04f1c 100644 > --- a/arch/riscv/boot/dts/microchip/Makefile > +++ b/arch/riscv/boot/dts/microchip/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb > obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) > diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi > new file mode 100644 > index 000000000000..49380c428ec9 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi > @@ -0,0 +1,16 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020-2022 Microchip Technology Inc */ > + > +/ { > + fabric_clk3: fabric-clk3 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <62500000>; > + }; > + > + fabric_clk1: fabric-clk1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > +}; > diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts > new file mode 100644 > index 000000000000..8c635f3358a5 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts > @@ -0,0 +1,95 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020-2022 Microchip Technology Inc */ > + > +/dts-v1/; > + > +#include "mpfs.dtsi" > +#include "mpfs-polarberry-fabric.dtsi" > + > +/* Clock frequency (in Hz) of the rtcclk */ > +#define MTIMER_FREQ 1000000 > + > +/ { > + model = "Sundance PolarBerry"; > + compatible = "sundance,polarberry", "microchip,mpfs"; > + > + aliases { > + serial0 = &mmuart0; > + ethernet0 = &mac0; Looks like I got this wrong and it should be mac1 > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + cpus { > + timebase-frequency = ; > + }; > + > + ddrc_cache_lo: memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x2e000000>; > + status = "okay"; > + }; > + > + ddrc_cache_hi: memory@1000000000 { > + device_type = "memory"; > + reg = <0x10 0x00000000 0x0 0xC0000000>; > + status = "okay"; > + }; > +}; > + > +&refclk { > + clock-frequency = <125000000>; > +}; > + > +&mmuart0 { > + status = "okay"; > +}; > + > +&mmc { > + status = "okay"; > + bus-width = <4>; > + disable-wp; > + cap-sd-highspeed; > + cap-mmc-highspeed; > + card-detect-delay = <200>; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + sd-uhs-sdr12; > + sd-uhs-sdr25; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > +}; > + > +&mac1 { > + status = "okay"; > + phy-mode = "sgmii"; > + phy-handle = <&phy1>; > + phy1: ethernet-phy@5 { > + reg = <5>; > + ti,fifo-depth = <0x01>; Whitespace here needs fixing. > + }; > + phy0: ethernet-phy@4 { > + reg = <4>; > + ti,fifo-depth = <0x01>; > + }; > +}; > + > +&mac0 { > + status = "okay"; > + phy-mode = "sgmii"; > + phy-handle = <&phy0>; > +}; > + > +&rtc { > + status = "okay"; > +}; > + > +&mbox { > + status = "okay"; > +}; > + > +&syscontroller { > + status = "okay"; > +};