From: Vince Weaver <vincent.weaver@maine.edu>
To: linux-kernel@vger.kernel.org
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Stephane Eranian <eranian@gmail.com>
Subject: [patch] perf: use proper dTLB-load-misses event on Ivybridge
Date: Mon, 14 Jul 2014 15:33:25 -0400 (EDT) [thread overview]
Message-ID: <alpine.DEB.2.11.1407141528200.17214@vincent-weaver-1.umelst.maine.edu> (raw)
This was discussed back in February
https://lkml.org/lkml/2014/2/18/956
But I never saw a patch come out of it.
On Ivybridge we share the Sandybridge cache event tables, but the
dTLB-load-miss event is not compatible. Patch it up after
the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index adb02aa..f5784f0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2465,6 +2465,9 @@ __init int intel_pmu_init(void)
case 62: /* IvyBridge EP */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
+ /* dTLB-load-misses on IVB is different than SNB */
+ hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
+
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
sizeof(hw_cache_extra_regs));
next reply other threads:[~2014-07-14 19:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-14 19:33 Vince Weaver [this message]
2014-07-14 19:52 ` [patch] perf: use proper dTLB-load-misses event on Ivybridge Andi Kleen
2014-07-16 13:53 ` Vince Weaver
2014-07-16 19:19 ` [tip:perf/urgent] perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge tip-bot for Vince Weaver
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