From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933655AbbIVNvO (ORCPT ); Tue, 22 Sep 2015 09:51:14 -0400 Received: from www.linutronix.de ([62.245.132.108]:40791 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933313AbbIVNvK (ORCPT ); Tue, 22 Sep 2015 09:51:10 -0400 Date: Tue, 22 Sep 2015 15:50:30 +0200 (CEST) From: Thomas Gleixner To: Boris Brezillon cc: Ludovic Desroches , jason@lakedaemon.net, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, sasha.levin@oracle.com, linux-arm-kernel@lists.infradead.org, nicolas.ferre@atmel.com, alexandre.belloni@free-electrons.com, Wenyou.Yang@atmel.com Subject: Re: [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask In-Reply-To: <20150922135558.7be8ac1c@bbrezillon> Message-ID: References: <1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com> <20150922135558.7be8ac1c@bbrezillon> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001,URIBL_BLOCKED=0.001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 22 Sep 2015, Boris Brezillon wrote: > On Tue, 22 Sep 2015 12:27:08 +0200 (CEST) > Thomas Gleixner wrote: > > Why is this locking dgc->gc[0] and fiddling with some other generic > > chip? > > Actually, we always access the same set of registers for all irqs of the > domain, and thus need to take the same lock (I chose the one contained > in the first generic irqchip, but I guess it could work with the others > too, as long as we always take the same one) before accessing them > because the configuration is done in two steps: > > 1/ specify the irq line you want to configure > 2/ set the new configuration > > Regarding register accesses, all generic chips are configured to > point to the same registers, so accessing them from the 'base' generic > chip or from the generic chip attached to the irq_data struct is the > same, though I agree that using bgc would add some consistency to the > implementation. Fair enough. It just deserves a comment for the casual reader. Thanks, tglx