From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752811AbbKPRRw (ORCPT ); Mon, 16 Nov 2015 12:17:52 -0500 Received: from www.linutronix.de ([62.245.132.108]:42008 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751397AbbKPRRv (ORCPT ); Mon, 16 Nov 2015 12:17:51 -0500 Date: Mon, 16 Nov 2015 18:17:09 +0100 (CET) From: Thomas Gleixner To: Qais Yousef cc: linux-kernel@vger.kernel.org, jason@lakedaemon.net, marc.zyngier@arm.com, jiang.liu@linux.intel.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain In-Reply-To: <56407F3C.4060404@imgtec.com> Message-ID: References: <1446549181-31788-1-git-send-email-qais.yousef@imgtec.com> <1446549181-31788-11-git-send-email-qais.yousef@imgtec.com> <56407F3C.4060404@imgtec.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 9 Nov 2015, Qais Yousef wrote: > On 11/07/2015 02:51 PM, Thomas Gleixner wrote: > Generally it's hard to know whether a real device is connected to a hwirq or > not. I am saving a patch where we get a set of free hwirqs from DT as only the > SoC designer knows what hwirq are actually free and safe to use for IPI. I'll > send this patch with the DT IPI changes or the rproc driver that I will be > send once these changes are merged. > > The current code assumes that the last 2 * NR_CPUs hwirqs are always free to > use for Linux SMP. So what you're saying is that you cannot rely on the last X hwirqs being available for IPIs. That's insane and to my knowledge there is no hardware out there which does not reserve a consecutive IPI space. But nevertheless, lets look at the various (possible) requirements we have: 1) IPI as per_cpu interrupts Single hwirq represented by a single irq descriptor 2) IPI with consecutive mapping space No extra mapping from virq base to target cpu required as its just linear. Everything can be handled via the base virq. 3) IPI with random mapping space Seperate mapping virq base to target cpu is required. The obvious place to store it are the irq descriptors. That needs a bit different machinery for ipi_send_mask(), but it's not rocket science. > > That makes a lot of things simpler. You don't have to keep a mapping > > of the hwirq to the target cpu. You just can use the base hwirq and > > calculate the destination hwirq from there when sending an IPI > > (general Linux ones). The coprocessor one will just be a natural > > fallout. > > Are you suggesting here to remove the whole new mapping API from the > generic code or just that it's not necessary to use it in my case? Err. I'm saying that you did not make use of hierarchical domains. You just glued the IPI stuff sideways on the GIC. We certainly want the generic code for managing the allocation etc. > I'm confused here as well. Is this a complementary API or are you suggesting > replacing the one this patch introduces? Those are replacements. We just need to handle the random mapping case if we really need it. Thanks, tglx