From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758970AbcKCRD2 (ORCPT ); Thu, 3 Nov 2016 13:03:28 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:36155 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758858AbcKCRD1 (ORCPT ); Thu, 3 Nov 2016 13:03:27 -0400 Date: Thu, 3 Nov 2016 11:00:30 -0600 (MDT) From: Thomas Gleixner To: Grzegorz Andrejczuk cc: mingo@redhat.com, hpa@zytor.com, x86@kernel.org, bp@suse.de, dave.hansen@linux.intel.com, lukasz.daniluk@intel.com, james.h.cownie@intel.com, jacob.jun.pan@intel.com, Piotr.Luc@intel.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit In-Reply-To: <1477995290-25079-2-git-send-email-grzegorz.andrejczuk@intel.com> Message-ID: References: <1477995290-25079-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477995290-25079-2-git-send-email-grzegorz.andrejczuk@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote: > > +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ Oh well. I asked you to make that whole PHI thing go away. This is a feature which has nothing to do with PHI. It just happens to be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific. It's all about a feature which enables ring 3 mwait/monitor. > +#define MSR_MISC_FEATURE_ENABLES 0x00000140 > +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1 > +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT) > + You really try hard to get your crap behind me. Stop sending out half baken shit every other day without addressing my review comments. Your trust level approaches negative space. Thanks, tglx