From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933217AbcKHQ6E (ORCPT ); Tue, 8 Nov 2016 11:58:04 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:55525 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932237AbcKHQ6D (ORCPT ); Tue, 8 Nov 2016 11:58:03 -0500 Date: Tue, 8 Nov 2016 17:55:20 +0100 (CET) From: Thomas Gleixner To: Tan Jui Nee cc: mika.westerberg@linux.intel.com, heikki.krogerus@linux.intel.com, andriy.shevchenko@linux.intel.com, mingo@redhat.com, "H. Peter Anvin" , x86@kernel.org, ptyser@xes-inc.com, lee.jones@linaro.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, LKML , jonathan.yong@intel.com, ong.hock.yu@intel.com, Tony Luck , wan.ahmad.zainie.wan.mohamad@intel.com, yunying.sun@intel.com, Darren Hart Subject: Re: [PATCH v9 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's In-Reply-To: <1478595443-6306-2-git-send-email-jui.nee.tan@intel.com> Message-ID: References: <1478595443-6306-1-git-send-email-jui.nee.tan@intel.com> <1478595443-6306-2-git-send-email-jui.nee.tan@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 8 Nov 2016, Tan Jui Nee wrote: > There is already one and at least one more user coming which > require an access to Primary to Sideband bridge (P2SB) in order > to get IO or MMIO bar hidden by BIOS. > Create a driver to access P2SB for x86 devices. > > arch/x86/Kconfig | 4 ++ > arch/x86/include/asm/p2sb.h | 27 +++++++++++ > arch/x86/platform/intel/Makefile | 1 + > arch/x86/platform/intel/p2sb.c | 98 ++++++++++++++++++++++++++++++++++++++++ This really has nothing to do with architecture. It's a platform enablement driver and therefor should go into drivers/platform/x86 Cc'ed Darren who is responsible for this. Thanks, tglx