From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934022AbcLPIxc (ORCPT ); Fri, 16 Dec 2016 03:53:32 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:48875 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759627AbcLPIwy (ORCPT ); Fri, 16 Dec 2016 03:52:54 -0500 Date: Fri, 16 Dec 2016 09:50:04 +0100 (CET) From: Thomas Gleixner To: Andy Lutomirski cc: LKML , X86 ML , Peter Zijlstra , Kyle Huey , Andy Lutomirski Subject: Re: [patch 3/3] x86/process: Optimize TIF_NOTSC switch In-Reply-To: Message-ID: References: <20161215162648.061449202@linutronix.de> <20161215164240.904945084@linutronix.de> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 15 Dec 2016, Andy Lutomirski wrote: > On Thu, Dec 15, 2016 at 8:44 AM, Thomas Gleixner wrote: > > +static inline void cr4_toggle_bits(unsigned long mask) > > +{ > > + unsigned long cr4; > > + > > + cr4 = this_cpu_read(cpu_tlbstate.cr4); > > + cr4 ^= mask; > > + this_cpu_write(cpu_tlbstate.cr4, cr4); > > + __write_cr4(cr4); > > +} > > This scares me for the same reason as BTF, although this should at > least be less fragile. But how about: If that is fragile then all cr4 manipulation code is fragile because it relies on cpu_tlbstate.cr4. The TIF flag and that per cpu thing are kept in sync. Thanks, tglx