From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935350AbcLUU0k (ORCPT ); Wed, 21 Dec 2016 15:26:40 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:60167 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752026AbcLUU0i (ORCPT ); Wed, 21 Dec 2016 15:26:38 -0500 Date: Wed, 21 Dec 2016 21:23:40 +0100 (CET) From: Thomas Gleixner To: Grzegorz Andrejczuk cc: mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org, Piotr.Luc@intel.com, dave.hansen@linux.intel.com Subject: Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit In-Reply-To: <1482241726-27310-2-git-send-email-grzegorz.andrejczuk@intel.com> Message-ID: References: <1482241726-27310-1-git-send-email-grzegorz.andrejczuk@intel.com> <1482241726-27310-2-git-send-email-grzegorz.andrejczuk@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote: > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 78f3760..55ffae0 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -539,6 +539,12 @@ > #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 > #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) > > +/* MISC_FEATURE_ENABLES non-architectural features */ > +#define MSR_MISC_FEATURE_ENABLES 0x00000140 > + > +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1 > +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT) > + This last define is not used anywhere. I told you before, but addressing my review comments completely is an unduly burden, or what? Thanks, tglx