From: Thomas Gleixner <tglx@linutronix.de>
To: Kan Liang <kan.liang@intel.com>
Cc: peterz@infradead.org, mingo@redhat.com,
linux-kernel@vger.kernel.org, bp@alien8.de, acme@kernel.org,
eranian@google.com, jolsa@kernel.org, ak@linux.intel.com
Subject: Re: [PATCH V3 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions
Date: Tue, 28 Mar 2017 19:23:09 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.20.1703281904301.3616@nanos> (raw)
In-Reply-To: <alpine.DEB.2.20.1703280940150.3616@nanos>
On Tue, 28 Mar 2017, Thomas Gleixner wrote:
> On Mon, 27 Mar 2017, kan.liang@intel.com wrote:
>
> > From: Kan Liang <Kan.liang@intel.com>
> >
> > To flip a MSR bit on many CPUs or specific CPU, currently it has to do
> > read-modify-write operation on the MSR through rd/wrmsr_on_cpu(s).
> > It actually sends two IPIs to the given CPU.
>
> The IPIs are the least of the problems, really. The real problem is that
>
> rdmsr_on_cpu()
> wrmsr_on_cpu()
>
> is not atomic. That's what wants to be solved. The reduction of IPIs just a
> side effect.
>
> > #else /* CONFIG_SMP */
> > +static inline int msr_set_bit_on_cpu(unsigned int cpu, u32 msr, u8 bit)
> > +{
> > + return msr_set_bit(msr, bit);
> > +}
> > +
> > +static inline int msr_clear_bit_on_cpu(unsigned int cpu, u32 msr, u8 bit)
> > +{
> > + return msr_clear_bit(msr, bit);
> > +}
> > +
> > +static inline void msr_set_bit_on_cpus(const struct cpumask *mask, u32 msr, u8 bit)
> > +{
> > + msr_set_bit(msr, bit);
> > +}
> > +
> > +static inline void msr_clear_bit_on_cpus(const struct cpumask *mask, u32 msr, u8 bit)
> > +{
> > + msr_clear_bit(msr, bit);
> > +}
>
> This is utter crap because it's fundamentaly different from the SMP
> version.
>
> msr_set/clear_bit() are not protected by anyhting. And in your call site
> this is invoked from fully preemptible context. What protects against
> context switch and interrupts fiddling with DEBUGMSR?
And thinking more about that whole interface. It's just overkill.
diff --git a/arch/x86/lib/msr.c b/arch/x86/lib/msr.c
index d1dee753b949..35763927adaa 100644
--- a/arch/x86/lib/msr.c
+++ b/arch/x86/lib/msr.c
@@ -58,7 +58,7 @@ int msr_write(u32 msr, struct msr *m)
return wrmsrl_safe(msr, m->q);
}
-static inline int __flip_bit(u32 msr, u8 bit, bool set)
+int msr_flip_bit(u32 msr, u8 bit, bool set)
{
struct msr m, m1;
int err = -EINVAL;
@@ -85,6 +85,7 @@ static inline int __flip_bit(u32 msr, u8 bit, bool set)
return 1;
}
+EXPORT_SYMBOL_GPL(msr_flip_bit);
/**
* Set @bit in a MSR @msr.
@@ -96,7 +97,7 @@ static inline int __flip_bit(u32 msr, u8 bit, bool set)
*/
int msr_set_bit(u32 msr, u8 bit)
{
- return __flip_bit(msr, bit, true);
+ return msr_flip_bit(msr, bit, true);
}
/**
@@ -109,7 +110,7 @@ int msr_set_bit(u32 msr, u8 bit)
*/
int msr_clear_bit(u32 msr, u8 bit)
{
- return __flip_bit(msr, bit, false);
+ return msr_flip_bit(msr, bit, false);
}
#ifdef CONFIG_TRACEPOINTS
And in the driver:
static void flip_smm_bit(void *data)
{
int val = *(int *)data;
msr_flip_bit(DEBUGMSR, SMMBIT, val);
}
And in the write function:
smp_call_function(flip_smm_bit, &val, 1);
That avoids all the extra interfaces and requires less code and less
text foot print when unused .....
Thanks,
tglx
next prev parent reply other threads:[~2017-03-28 17:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-27 18:30 [PATCH V3 0/2] measure SMI cost (kernel) kan.liang
2017-03-27 18:30 ` [PATCH V3 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions kan.liang
2017-03-28 8:36 ` Thomas Gleixner
2017-03-28 17:23 ` Thomas Gleixner [this message]
2017-03-28 17:38 ` Liang, Kan
2017-03-28 18:34 ` Thomas Gleixner
2017-03-27 18:30 ` [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI kan.liang
2017-03-28 8:42 ` Thomas Gleixner
2017-03-28 13:23 ` Liang, Kan
2017-03-28 17:03 ` Thomas Gleixner
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