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From: matthew.gerlach@linux.intel.com
To: Marek Vasut <marek.vasut@gmail.com>
Cc: vndao@altera.com, dwmw2@infradead.org,
	computersforpeace@gmail.com, boris.brezillon@free-electrons.com,
	richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,
	mark.rutland@arm.com, linux-mtd@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	gregkh@linuxfoundation.org, davem@davemloft.net,
	mchehab@kernel.org, linux-fpga@vger.kernel.org,
	tien.hock.loh@intel.com, hean.loong.ong@intel.com
Subject: Re: [PATCH v2 2/3] mtd: spi-nor: Altera ASMI Parallel II IP Core
Date: Wed, 11 Oct 2017 10:00:37 -0700 (PDT)	[thread overview]
Message-ID: <alpine.DEB.2.20.1710110956260.2194@mgerlach-VirtualBox> (raw)
In-Reply-To: <deae5a9f-4301-c7de-b265-b09292f8da15@gmail.com>



On Tue, 10 Oct 2017, Marek Vasut wrote:

> On 09/20/2017 08:28 PM, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> This patch adds support for a spi-nor, platform driver for the
>> Altera ASMI Parallel II IP Core.  The intended use case is to be able
>> to update the flash used to load a FPGA at power up with mtd-utils.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v2:
>>     minor checkpatch fixing by Wu Hao <hao.wu@intel.com>
>>     Use read_dummy value as suggested by Cyrille Pitchen.
>>     Don't assume 4 byte addressing (Cryille Pichecn and Marek Vasut).
>>     Fixed #define indenting as suggested by Marek Vasut.
>>     Added units to timer values as suggested by Marek Vasut.
>>     Use io(read|write)8_rep() as suggested by Marek Vasut.
>>     Renamed function prefixed with __ as suggested by Marek Vasut.
>
> [...]
>
>> +#define QSPI_ACTION_REG			0
>> +#define QSPI_ACTION_RST			BIT(0)
>> +#define QSPI_ACTION_EN			BIT(1)
>> +#define QSPI_ACTION_SC			BIT(2)
>> +#define QSPI_ACTION_CHIP_SEL_SFT	4
>> +#define QSPI_ACTION_DUMMY_SFT		8
>> +#define QSPI_ACTION_READ_BACK_SFT	16
>> +
>> +#define QSPI_FIFO_CNT_REG		4
>> +#define QSPI_FIFO_DEPTH			0x200
>> +#define QSPI_FIFO_CNT_MSK		0x3ff
>> +#define QSPI_FIFO_CNT_RX_SFT		0
>> +#define QSPI_FIFO_CNT_TX_SFT		12
>> +
>> +#define QSPI_DATA_REG			0x8
>> +
>> +#define QSPI_POLL_TIMEOUT_US		10000000
>
> 10 s poll timeout ? :)

Hi Marek,

The 10s timeout is fairly arbitrary.  In other words, I pulled it out of 
thin air.  Can you suggest a better timeout?  From a practical standpoint 10s 
seemed to be much better than no timeout when I was debugging bad FPGA 
images.  Without a timeout I was hanging the system when the FPGA image 
failed.  With this timeout, we get a nice message and Linux keeps running 
happily.

Thanks for the feedback,

Matthew Gerlach

>
>> +#define QSPI_POLL_INTERVAL_US		 5 >> + >> +struct 
altera_asmip2 { >
> [...]
>
> Otherwise looks good
>
> -- 
> Best regards,
> Marek Vasut
>

  reply	other threads:[~2017-10-11 17:01 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-20 18:28 [PATCH v2 0/3] Altera ASMI Parallel II IP Core matthew.gerlach
2017-09-20 18:28 ` [PATCH v2 1/3] dt-bindings: mtd: " matthew.gerlach
2017-09-27 21:52   ` Rob Herring
2017-09-20 18:28 ` [PATCH v2 2/3] mtd: spi-nor: " matthew.gerlach
2017-10-10  9:24   ` Marek Vasut
2017-10-11 17:00     ` matthew.gerlach [this message]
2017-10-11 21:06       ` Marek Vasut
2017-10-13 19:24         ` matthew.gerlach
2017-09-20 18:28 ` [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg matthew.gerlach
2017-10-10 19:23   ` Cyrille Pitchen
2017-10-16 18:41     ` matthew.gerlach
2017-10-10  0:49 ` [PATCH v2 0/3] Altera ASMI Parallel II IP Core matthew.gerlach

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