From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933907AbdKAVZb (ORCPT ); Wed, 1 Nov 2017 17:25:31 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:51283 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933625AbdKAVZ3 (ORCPT ); Wed, 1 Nov 2017 17:25:29 -0400 Date: Wed, 1 Nov 2017 22:25:26 +0100 (CET) From: Thomas Gleixner To: Dave Hansen cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, moritz.lipp@iaik.tugraz.at, daniel.gruss@iaik.tugraz.at, michael.schwarz@iaik.tugraz.at, luto@kernel.org, torvalds@linux-foundation.org, keescook@google.com, hughd@google.com, x86@kernel.org Subject: Re: [PATCH 04/23] x86, tlb: make CR4-based TLB flushes more robust In-Reply-To: <20171031223154.67F15B2A@viggo.jf.intel.com> Message-ID: References: <20171031223146.6B47C861@viggo.jf.intel.com> <20171031223154.67F15B2A@viggo.jf.intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 31 Oct 2017, Dave Hansen wrote: > Our CR4-based TLB flush currently requries global pages to be > supported *and* enabled. But, we really only need for them to be > supported. Make the code more robust by alllowing X86_CR4_PGE to > clear as well as set. That's not what the patch is actually doing. > cr4 = this_cpu_read(cpu_tlbstate.cr4); > - /* clear PGE */ > - native_write_cr4(cr4 & ~X86_CR4_PGE); > - /* write old PGE again and flush TLBs */ > + /* > + * This function is only called on systems that support X86_CR4_PGE > + * and where always set X86_CR4_PGE. Warn if we are called without > + * PGE set. > + */ > + WARN_ON_ONCE(!(cr4 & X86_CR4_PGE)); Because if CR4_PGE is not set, this warning triggers. So this defeats the toggle mode you are implementing. > + /* > + * Architecturally, any _change_ to X86_CR4_PGE will fully flush the > + * TLB of all entries including all entries in all PCIDs and all > + * global pages. Make sure that we _change_ the bit, regardless of > + * whether we had X86_CR4_PGE set in the first place. > + */ > + native_write_cr4(cr4 ^ X86_CR4_PGE); > + /* Put original CR3 value back: */ That want's to be CR4. Restoring CR3 to CR4 might be suboptimal. > native_write_cr4(cr4); Thanks, tglx