From: Thomas Gleixner <tglx@linutronix.de>
To: Christoph Hellwig <hch@infradead.org>
Cc: Atish Patra <atish.patra@wdc.com>,
palmer@sifive.com, linux-riscv@lists.infradead.org,
mark.rutland@arm.com, robh@kernel.org, Damien.LeMoal@wdc.com,
marc.zyngier@arm.com, anup@brainfault.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC 3/3] RISC-V: Remove per cpu clocksource
Date: Mon, 17 Sep 2018 16:52:44 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1809171638560.16580@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180917143550.GC15588@infradead.org>
On Mon, 17 Sep 2018, Christoph Hellwig wrote:
> I think only having one clocksource is indeed the right thing.
>
> But that makes the whole TIMER_OF_DECLARE for each hart (cpu core for
> those not RISC-V savvy) even more questionable than it already is.
>
> I think we should just initialize the clocksource directly as it is
> architectually guaranteed to exist. Below is a completely untested
> (not even compiled) version of your patch that does what I think
> we should be doing here. But I'd rather hear from more timer and/or
> DT savvy folks before proceeding.
If this really does not need configuration and all actual implementations
are not "allowed" to screw the timer up, then this surely can do without
DT.
Just for the record, this would be the first (architected) timer ever which
just works. I'm having a hard time to believe this, but I'd certainly
welcome it.
> -TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
> +core_initcall(riscv_timer_init);
Are you sure that core_initcall is not too late?
Thanks,
tglx
next prev parent reply other threads:[~2018-09-17 14:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-14 21:54 [RFC 0/3] Timer code cleanup Atish Patra
2018-09-14 21:54 ` [RFC 1/3] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-09-17 14:20 ` Christoph Hellwig
2018-09-18 2:26 ` Atish Patra
2018-09-14 21:54 ` [RFC 2/3] RISC-V:Support per-hart timebase-frequency Atish Patra
2018-09-17 14:23 ` Christoph Hellwig
2018-09-18 2:23 ` Atish Patra
2018-09-29 0:20 ` Palmer Dabbelt
2018-09-14 21:54 ` [RFC 3/3] RISC-V: Remove per cpu clocksource Atish Patra
2018-09-17 14:35 ` Christoph Hellwig
2018-09-17 14:52 ` Thomas Gleixner [this message]
2018-09-17 15:01 ` Christoph Hellwig
2018-09-17 15:04 ` Thomas Gleixner
2018-09-17 15:54 ` Anup Patel
2018-09-17 18:32 ` Atish Patra
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