From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4F17C43382 for ; Thu, 27 Sep 2018 14:49:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 916FA21547 for ; Thu, 27 Sep 2018 14:49:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 916FA21547 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=linutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728379AbeI0VIL (ORCPT ); Thu, 27 Sep 2018 17:08:11 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:52200 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727404AbeI0VIK (ORCPT ); Thu, 27 Sep 2018 17:08:10 -0400 Received: from p5492e4c1.dip0.t-ipconnect.de ([84.146.228.193] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1g5XbS-0005ZK-Q7; Thu, 27 Sep 2018 16:49:18 +0200 Date: Thu, 27 Sep 2018 16:49:18 +0200 (CEST) From: Thomas Gleixner To: Peter Zijlstra cc: Andi Kleen , Dave Hansen , kan.liang@linux.intel.com, mingo@redhat.com, len.brown@intel.com, linux-kernel@vger.kernel.org, x86@kernel.org Subject: Re: [PATCH] x86/cpu: Rename Denverton and Gemini Lake In-Reply-To: <20180927142519.GB3439@hirez.programming.kicks-ass.net> Message-ID: References: <1533662247-17575-1-git-send-email-kan.liang@linux.intel.com> <1b7cb461-5321-86cf-3031-5ff545c3dc42@linux.intel.com> <20180807174851.GJ2494@hirez.programming.kicks-ass.net> <20180807183736.GR4238@tassilo.jf.intel.com> <20180807221725.GU4238@tassilo.jf.intel.com> <20180927142519.GB3439@hirez.programming.kicks-ass.net> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 27 Sep 2018, Peter Zijlstra wrote: > On Wed, Aug 08, 2018 at 07:14:52AM +0200, Thomas Gleixner wrote: > > > We have that for the big cores as well: > > > > #define INTEL_FAM6_HASWELL_CORE 0x3C > > #define INTEL_FAM6_HASWELL_X 0x3F > > #define INTEL_FAM6_HASWELL_ULT 0x45 > > #define INTEL_FAM6_HASWELL_GT3E 0x46 > > > > Why would we treat ATOM differently? It's all the same scheme: > > > > SILVERMONT_CLIENT 0x37 Baytrail, Valleyview > > SILVERMONT_SERVER 0x40 Avaton, Rangely > > > > and on goldmont it's not any different. > > > > We really want one scheme for both Core and ATOM and not randomly picked > > different ones. For the kernel (aside of some peripheral stuff) the most > > interesting information is the UARCH plus the extra features which are > > enabled on a particular SoC. > > > > The current naming scheme e.g. for SILVERMONT is utter crap because the 1/2 > > variants are in fact CLIENT/SERVER and the comment in the header file, that > > there is no better name, is just silly. > > OK, I spend a lot of time googling various things and came up with the > below. TL;DR: > > /* "Small Core" Processors (Atom) */ > > #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ > #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ > > #define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ > #define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ > #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ > > #define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ > #define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */ > #define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ > > #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ > #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ > > #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ > #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denvertor */ > #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ Thanks for doing that! > --- > Subject: x86/cpu: Sanitize FAM6_ATOM naming > From: Peter Zijlstra > Date: Tue, 7 Aug 2018 10:17:27 -0700 > > Going primarily by: > > https://en.wikipedia.org/wiki/List_of_Intel_Atom_microprocessors#Silvermont_microarchitecture > > with additional information gleaned from other related pages; notably: > > - Bonnell shrink was called Saltwell > - Moorefield is the Merriefield refresh which makes it Airmont > > The general naming scheme is: FAM6_ATOM_UARCH_SOCTYPE > > Cc: x86@kernel.org > Cc: mingo@redhat.com > Cc: ak@linux.intel.com > Cc: tglx@linutronix.de > Cc: dave.hansen@linux.intel.com > Cc: len.brown@intel.com > Signed-off-by: Peter Zijlstra (Intel) Which way do we route that? Thanks, tglx