From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
H Peter Anvin <hpa@zytor.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Dave Hansen <dave.hansen@intel.com>,
Ashok Raj <ashok.raj@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Christopherson Sean J <sean.j.christopherson@intel.com>,
Kalle Valo <kvalo@codeaurora.org>,
Michael Chan <michael.chan@broadcom.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
kvm@vger.kernel.org, netdev@vger.kernel.org,
linux-wireless@vger.kernel.org
Subject: Re: [PATCH v7 14/21] x86/split_lock: Enable split lock detection by default
Date: Thu, 18 Apr 2019 00:41:52 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1904180019390.3174@nanos.tec.linutronix.de> (raw)
In-Reply-To: <1555536851-17462-15-git-send-email-fenghua.yu@intel.com>
On Wed, 17 Apr 2019, Fenghua Yu wrote:
> A split locked access locks bus and degrades overall memory access
> performance. When split lock detection feature is enumerated, enable
> the feature by default to find any split lock issue.
>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> ---
> arch/x86/kernel/cpu/intel.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 997d683d3c27..6a692d215bef 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -34,6 +34,8 @@
> DEFINE_PER_CPU(u64, msr_test_ctl_cache);
> EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache);
>
> +static bool split_lock_detect_enable;
> +
> /*
> * Just in case our CPU detection goes bad, or you have a weird system,
> * allow a way to override the automatic disabling of MPX.
> @@ -164,6 +166,23 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
> return false;
> }
>
> +static void split_lock_update_msr(void *__unused)
> +{
> + if (split_lock_detect_enable) {
> + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT);
> + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT);
> + } else {
> + msr_clear_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT);
> + this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT);
> + }
Nothing in this file initializes msr_test_ctl_cache explicitely. Register
caching always requires to read the register and store it in the cache
before doing anything with it. Nothing guarantees that all bits in that MSR
are 0 by default forever.
And once you do that _before_ calling split_lock_update_msr() then you can
spare the RMW in that function.
> +static void init_split_lock_detect(struct cpuinfo_x86 *c)
> +{
> + if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT))
> + split_lock_update_msr(NULL);
> +}
> +
> static void early_init_intel(struct cpuinfo_x86 *c)
> {
> u64 misc_enable;
> @@ -661,6 +680,8 @@ static void init_intel(struct cpuinfo_x86 *c)
> {
> early_init_intel(c);
>
> + init_split_lock_detect(c);
Sigh. Why needs this to be squeezed in the middle of the whole enumeration
stuff? Just because....
init_intel_misc_features() is called at the end and it does also MSR
caching etc. So down there is the right place.
> +
> intel_workarounds(c);
>
> /*
> @@ -1032,9 +1053,22 @@ static const struct cpu_dev intel_cpu_dev = {
>
> cpu_dev_register(intel_cpu_dev);
>
> +#undef pr_fmt
> +#define pr_fmt(fmt) "x86/split lock detection: " fmt
> +
> +static void show_split_lock_detection_info(void)
> +{
> + if (split_lock_detect_enable)
> + pr_info("enabled\n");
> + else
> + pr_info("disabled\n");
This function is truly useful. The else path is never invoked. See the call
site below.
> +}
> +
> static void __init set_split_lock_detect(void)
> {
> setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
> + split_lock_detect_enable = true;
> + show_split_lock_detection_info();
> }
Oh well.
Thanks,
tglx
next prev parent reply other threads:[~2019-04-17 22:42 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-17 21:33 [PATCH v7 00/21] x86/split_lock: Enable split lock detection Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 01/21] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 02/21] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 03/21] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 04/21] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-04-18 9:20 ` David Laight
2019-04-18 11:08 ` David Laight
2019-04-18 11:49 ` Thomas Gleixner
2019-04-18 13:14 ` David Laight
2019-04-18 13:26 ` David Laight
2019-04-17 21:33 ` [PATCH v7 05/21] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 06/21] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 07/21] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 08/21] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-04-17 21:33 ` [PATCH v7 09/21] x86/split_lock: Define MSR TEST_CTL register Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 10/21] x86/split_lock: Define per CPU variable to cache MSR TEST_CTL Fenghua Yu
2019-04-17 22:14 ` Thomas Gleixner
2019-04-18 1:28 ` Fenghua Yu
2019-04-18 6:31 ` Thomas Gleixner
2019-04-17 21:34 ` [PATCH v7 11/21] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 12/21] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 13/21] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 14/21] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-04-17 22:41 ` Thomas Gleixner [this message]
2019-04-17 21:34 ` [PATCH v7 15/21] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-04-17 22:47 ` Thomas Gleixner
2019-04-18 0:57 ` Fenghua Yu
2019-04-18 6:41 ` Thomas Gleixner
2019-04-23 20:48 ` Fenghua Yu
2019-04-24 13:45 ` David Laight
2019-04-17 21:34 ` [PATCH v7 16/21] x86/split_lock: Document the new sysfs file for split lock detection Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 17/21] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-04-17 23:05 ` Thomas Gleixner
2019-04-17 21:34 ` [PATCH v7 18/21] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-04-17 23:19 ` Thomas Gleixner
2019-04-17 23:47 ` Fenghua Yu
2019-04-18 6:16 ` Thomas Gleixner
2019-04-17 21:34 ` [PATCH v7 19/21] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 20/21] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-04-17 21:34 ` [PATCH v7 21/21] x86/clearcpuid: Change document for kernel option clearcpuid Fenghua Yu
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