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From: Thomas Gleixner <tglx@linutronix.de>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
	Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
	Bandan Das <bsd@redhat.com>
Subject: Re: Linux 5.3-rc7
Date: Sat, 7 Sep 2019 16:29:19 +0200 (CEST)
Message-ID: <alpine.DEB.2.21.1909071628420.1902@nanos.tec.linutronix.de> (raw)
In-Reply-To: <156785100521.13300.14461504732265570003@skylake-alporthouse-com>

On Sat, 7 Sep 2019, Chris Wilson wrote:
> Quoting Linus Torvalds (2019-09-02 18:28:26)
> > Bandan Das:
> >       x86/apic: Include the LDR when clearing out APIC registers
> 
> Apologies if this is known already, I'm way behind on email.
> 
> I've bisected
> 
> [   18.693846] smpboot: CPU 0 is now offline
> [   19.707737] smpboot: Booting Node 0 Processor 0 APIC 0x0
> [   29.707602] smpboot: do_boot_cpu failed(-1) to wakeup CPU#0
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/igt@perf_pmu@cpu-hotplug.html
> 
> to 558682b52919. (Reverts cleanly and fixes the problem.)
> 
> I'm guessing that this is also behind the suspend failures, missing
> /dev/cpu/0/msr, and random perf_event_open() failures we have observed
> in our CI since -rc7 across all generations of Intel cpus.

So is this on bare metal or in a VM?

Thanks,

	tglx

  reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-02 17:28 Linus Torvalds
2019-09-07 10:10 ` Chris Wilson
2019-09-07 14:29   ` Thomas Gleixner [this message]
2019-09-07 14:41     ` Chris Wilson
2019-09-07 15:00       ` Thomas Gleixner
2019-09-07 15:24         ` Chris Wilson
2019-09-07 20:12           ` Thomas Gleixner
2019-09-07 19:17         ` Linus Torvalds
2019-09-07 19:27           ` Linus Torvalds
2019-09-09 13:54             ` Bandan Das
2019-09-07 20:44           ` Thomas Gleixner
2019-09-07 21:13             ` Linus Torvalds
2019-09-08 11:02               ` Sasha Levin

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