From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA2DBECE58E for ; Thu, 17 Oct 2019 12:30:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A8D7F2064B for ; Thu, 17 Oct 2019 12:30:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394175AbfJQMaC (ORCPT ); Thu, 17 Oct 2019 08:30:02 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:52857 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728190AbfJQMaC (ORCPT ); Thu, 17 Oct 2019 08:30:02 -0400 Received: from [5.158.153.52] (helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iL4uY-0007rm-1f; Thu, 17 Oct 2019 14:29:46 +0200 Date: Thu, 17 Oct 2019 14:29:45 +0200 (CEST) From: Thomas Gleixner To: Paolo Bonzini cc: Xiaoyao Li , Sean Christopherson , Fenghua Yu , Ingo Molnar , Borislav Petkov , H Peter Anvin , Peter Zijlstra , Andrew Morton , Dave Hansen , Radim Krcmar , Ashok Raj , Tony Luck , Dan Williams , Sai Praneeth Prakhya , Ravi V Shankar , linux-kernel , x86 , kvm@vger.kernel.org Subject: [RFD] x86/split_lock: Request to Intel In-Reply-To: Message-ID: References: <1560897679-228028-1-git-send-email-fenghua.yu@intel.com> <1560897679-228028-10-git-send-email-fenghua.yu@intel.com> <20190626203637.GC245468@romley-ivt3.sc.intel.com> <20190925180931.GG31852@linux.intel.com> <3ec328dc-2763-9da5-28d6-e28970262c58@redhat.com> <57f40083-9063-5d41-f06d-fa1ae4c78ec6@redhat.com> <8808c9ac-0906-5eec-a31f-27cbec778f9c@intel.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The more I look at this trainwreck, the less interested I am in merging any of this at all. The fact that it took Intel more than a year to figure out that the MSR is per core and not per thread is yet another proof that this industry just works by pure chance. There is a simple way out of this misery: Intel issues a microcode update which does: 1) Convert the OR logic of the AC enable bit in the TEST_CTRL MSR to AND logic, i.e. when one thread disables AC it's automatically disabled on the core. Alternatively it supresses the #AC when the current thread has it disabled. 2) Provide a separate bit which indicates that the AC enable logic is actually AND based or that #AC is supressed when the current thread has it disabled. Which way I don't really care as long as it makes sense. If that's not going to happen, then we just bury the whole thing and put it on hold until a sane implementation of that functionality surfaces in silicon some day in the not so foreseeable future. Seriously, this makes only sense when it's by default enabled and not rendered useless by VIRT. Otherwise we never get any reports and none of the issues are going to be fixed. Thanks, tglx