From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B750BC433E0 for ; Thu, 11 Feb 2021 23:10:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F9FB64E05 for ; Thu, 11 Feb 2021 23:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229895AbhBKXKF (ORCPT ); Thu, 11 Feb 2021 18:10:05 -0500 Received: from angie.orcam.me.uk ([157.25.102.26]:47402 "EHLO angie.orcam.me.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbhBKXKC (ORCPT ); Thu, 11 Feb 2021 18:10:02 -0500 Received: by angie.orcam.me.uk (Postfix, from userid 500) id 2AC2B9200B4; Fri, 12 Feb 2021 00:09:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id 242799200B3; Fri, 12 Feb 2021 00:09:20 +0100 (CET) Date: Fri, 12 Feb 2021 00:09:20 +0100 (CET) From: "Maciej W. Rozycki" To: Thomas Gleixner cc: Linus Torvalds , Serge Belyshev , Dirk Gouders , =?UTF-8?Q?Micka=C3=ABl_Sala=C3=BCn?= , LKML , Alexandre Belloni , Jason Gunthorpe , Miroslav Lichvar , John Stultz , Prarit Bhargava , Alessandro Zummo , linux-rtc@vger.kernel.org, Peter Zijlstra Subject: Re: [PATCH V2] rtc: mc146818: Dont test for bit 0-5 in Register D In-Reply-To: <87wnvrbmqx.fsf@nanos.tec.linutronix.de> Message-ID: References: <20201206214613.444124194@linutronix.de> <20201206220541.594826678@linutronix.de> <19a7753c-c492-42e4-241a-8a052b32bb63@digikod.net> <871re7hlsg.fsf@nanos.tec.linutronix.de> <98cb59e8-ecb4-e29d-0b8f-73683ef2bee7@digikod.net> <87y2gfg18p.fsf@nanos.tec.linutronix.de> <87tur3fx7w.fsf@nanos.tec.linutronix.de> <877dnrc2sv.fsf@depni.sinp.msu.ru> <8735yfd2q4.fsf@nanos.tec.linutronix.de> <87zh0nbnha.fsf@nanos.tec.linutronix.de> <87wnvrbmqx.fsf@nanos.tec.linutronix.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 1 Feb 2021, Thomas Gleixner wrote: > >> While it cures the problem on the reporters machine it breaks machines > >> with Intel chipsets which use bit 0-5 of the D register. So check only > >> for bit 6 being 0 which is the case on these Intel machines as well. > > > > This looks fine, but it might also be worth it simply just checking > > for the only really special value: 0xff, and going "ok, that looks > > like missing hardware". > > > > That's what a few other drivers historically do in their probing > > routines, so it's not unheard of (ie you can find drivers doing that > > kind of > > > > /* If we read 0xff from the LSR, there is no UART here. */ > > if (inb(.. port ..) == 0xff) > > > > in their init routines. > > > > Not a big deal either way, I just think it would be more in like with > > what other places do in similar situations > > Yeah, we can do that as well. Either way is fine. Given that evidently vendors appear to start playing with 146818 clones it may be worth it to peek at the D and the C register and checking they are not 0xff both at a time for robustness before concluding no RTC is present. The C register is supposed to hold zeros in bits 3:0. A read of the C register will drop interrupt bits, but I guess it does not matter at the probe time. FWIW, Maciej