From: "Maciej W. Rozycki" <firstname.lastname@example.org> To: Nikolai Zhubr <email@example.com> Cc: Bjorn Helgaas <firstname.lastname@example.org>, Thomas Gleixner <email@example.com>, Ingo Molnar <firstname.lastname@example.org>, Borislav Petkov <email@example.com>, "H. Peter Anvin" <firstname.lastname@example.org>, Arnd Bergmann <email@example.com>, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org Subject: Re: [PATCH v2] x86/PCI: Handle PIRQ routing tables with no router device given Date: Fri, 9 Jul 2021 01:35:47 +0200 (CEST) [thread overview] Message-ID: <alpine.DEB.email@example.com> (raw) In-Reply-To: <60E77EBF.firstname.lastname@example.org> On Fri, 9 Jul 2021, Nikolai Zhubr wrote: > > Have you tried contacting Nvidia about your ALI chipset? Back in the day > > I tried to avoid undocumented stuff and Intel was reasonably open about > > most of their chipsets. > > Well, being neither their customer nor a kernel developer, I'm not sure my > request would be considered serious. Anyway, probably I'll give it a try a bit > later when I have an opportunity to dismount this board for more comfortable > testing. It never hurts asking. At worst you'll be ignored, and at the second worst they'll say nay. They may have lost it too. > I was also going to try to modify its BIOS to remove some unwanted > behaviour unrelated to IRQs, and it might happen that I also discover > something about PCI handling along with (It is just 64k size, after all, and I > have a 8086 debugger) Umm, the board may be old enough not to play any tricks with the BIOS, but mind that at reset x86 starts in the flat mode from 0xfffffff0 and the contents of ROM there may not be what you see at 0xf000:0xfff0 later on. I once worked on a project where I had an opportunity to access the BIOS at the reset vector (and poke at CPU registers, run, stop, single-step it, place hardware breakpoints, etc.) using GDB over JTAG with an Intel Atom board. It was an interesting experience, but sadly most x86 hardware does not have the capability let alone a JTAG connector (called XDP or eXtended Debug Port in Intel-speak) to attach a probe to. You may try disassembling the PCI BIOS 2.1 service however. Maciej
prev parent reply other threads:[~2021-07-08 23:35 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-06 11:30 Maciej W. Rozycki 2021-07-08 16:25 ` Nikolai Zhubr 2021-07-08 20:45 ` Maciej W. Rozycki 2021-07-08 22:39 ` Nikolai Zhubr 2021-07-08 23:35 ` Maciej W. Rozycki [this message]
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=alpine.DEB.email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --email@example.com \ --firstname.lastname@example.org \ --subject='Re: [PATCH v2] x86/PCI: Handle PIRQ routing tables with no router device given' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).