From: Paul Walmsley <paul.walmsley@sifive.com>
To: Christoph Hellwig <hch@lst.de>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH 09/12] riscv: clear the instruction cache and all registers when booting
Date: Wed, 13 Nov 2019 23:45:10 -0800 (PST) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1911132344530.11342@viisi.sifive.com> (raw)
In-Reply-To: <20191028121043.22934-10-hch@lst.de>
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> When we get booted we want a clear slate without any leaks from previous
> supervisors or the firmware. Flush the instruction cache and then clear
> all registers to known good values. This is really important for the
> upcoming nommu support that runs on M-mode, but can't really harm when
> running in S-mode either. Vaguely based on the concepts from opensbi.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
Thanks, queued for v5.5-rc1.
- Paul
next prev parent reply other threads:[~2019-11-14 7:45 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 12:10 RISC-V nommu support v6 Christoph Hellwig
2019-10-28 12:10 ` [PATCH 01/12] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-11-05 17:56 ` Paul Walmsley
2019-11-05 17:57 ` Paul Walmsley
2019-11-05 18:02 ` Marc Zyngier
2019-11-12 10:38 ` Thomas Gleixner
2019-11-14 7:30 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 02/12] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-11-14 7:31 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 03/12] riscv: poison SBI calls " Christoph Hellwig
2019-10-31 23:55 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 04/12] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-31 20:49 ` Paul Walmsley
2019-10-31 23:56 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 05/12] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-31 23:57 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 06/12] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-11-05 18:01 ` Paul Walmsley
2019-11-12 10:39 ` Thomas Gleixner
2019-11-17 23:06 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 07/12] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-28 12:10 ` [PATCH 08/12] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-28 12:10 ` [PATCH 09/12] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-11-14 7:45 ` Paul Walmsley [this message]
2019-10-28 12:10 ` [PATCH 10/12] riscv: add nommu support Christoph Hellwig
2019-11-17 23:13 ` Paul Walmsley
2019-12-16 22:03 ` David Abdurachmanov
2019-12-17 3:18 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 11/12] riscv: provide a flat image loader Christoph Hellwig
2019-11-17 23:14 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-30 20:21 ` RISC-V nommu support v6 Paul Walmsley
2019-10-31 15:52 ` Christoph Hellwig
2019-10-31 20:13 ` Paul Walmsley
2019-11-23 2:19 ` Paul Walmsley
2019-12-11 8:42 ` Greentime Hu
2020-02-12 12:19 ` Greentime Hu
2019-11-11 9:47 ` Christoph Hellwig
2019-11-11 17:02 ` Paul Walmsley
2019-11-13 13:18 ` Christoph Hellwig
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