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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Christoph Hellwig <hch@lst.de>
Cc: iommu@lists.linux-foundation.org,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Paul Burton <paul.burton@mips.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/6] dma-mapping: merge direct and noncoherent ops
Date: Wed, 31 Oct 2018 16:31:40 +0000 (GMT)	[thread overview]
Message-ID: <alpine.LFD.2.21.1810311559590.20378@eddie.linux-mips.org> (raw)
In-Reply-To: <alpine.LFD.2.21.1810311414200.20378@eddie.linux-mips.org>

On Wed, 31 Oct 2018, Maciej W. Rozycki wrote:

> > All the cache maintainance is already stubbed out when not enabled,
> > but merging the two allows us to nicely handle the case where
> > cache maintainance is required for some devices, but not others.
> 
>  FYI, you commit bc3ec75de545 ("dma-mapping: merge direct and noncoherent 
> ops") has caused:
> 
> fddi0: DMA command request failed!
> fddi0: Adapter open failed!
> 
> with the `defxx' driver on my R4400SC TURBOchannel DECstation (but not the 
> R3400 one) and consequently the interface does not work anymore.  Both are 
> non-coherent cache systems, however the R3400 implements the write-through 
> policy while the policy of the R4400SC is write-back (it also has 1MiB of 
> secondary cache), which I suspect is the reason of the difference.

 Doh!  It would have helped if I actually had the right adapter installed 
in the R3400 box.  I've got a spare one, which I have now plugged in there 
and the R3400 actually shows the same issue as the R4400SC does.  So this 
has nothing to do WRT write-through vs write-back.

 Hmm, in `dfx_hw_dma_cmd_req' the driver polls the consumer block (which 
is write-only by the adapter and read-only by the host, except for the 
initialisation time before adapter's DMA engines have been started, and 
write-through vs write-back indeed does not matter for this kind of use) 
and there's no DMA synchronisation whatsoever in that.

 However the block has been allocated with `dma_zalloc_coherent', which 
means no synchronisation is supposed to be required.  For non-coherent 
cache systems that essentially means an uncached memory allocation.

  Maciej

  reply	other threads:[~2018-10-31 16:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-14  9:58 merge dma_direct_ops and dma_noncoherent_ops v3 Christoph Hellwig
2018-09-14  9:58 ` [PATCH 1/6] dma-mapping: add the missing ARCH_HAS_SYNC_DMA_FOR_CPU_ALL declaration Christoph Hellwig
2018-09-14  9:58 ` [PATCH 2/6] MIPS: don't select DMA_MAYBE_COHERENT from DMA_PERDEV_COHERENT Christoph Hellwig
2018-09-14  9:58 ` [PATCH 3/6] dma-mapping: move the dma_coherent flag to struct device Christoph Hellwig
2018-09-14  9:58 ` [PATCH 4/6] dma-mapping: merge direct and noncoherent ops Christoph Hellwig
2018-10-31 14:24   ` Maciej W. Rozycki
2018-10-31 16:31     ` Maciej W. Rozycki [this message]
2018-10-31 20:32       ` Christoph Hellwig
2018-10-31 20:50         ` Maciej W. Rozycki
2018-11-01  5:13           ` Christoph Hellwig
2018-11-01  7:54             ` [PATCH] MIPS: Fix `dma_alloc_coherent' returning a non-coherent allocation Maciej W. Rozycki
2018-11-01  8:33               ` Christoph Hellwig
2018-11-01 14:30                 ` Maciej W. Rozycki
2018-11-05 18:10               ` Paul Burton
2018-09-14  9:58 ` [PATCH 5/6] dma-mapping: consolidate the dma mmap implementations Christoph Hellwig
2018-09-14  9:58 ` [PATCH 6/6] dma-mapping: support non-coherent devices in dma_common_get_sgtable Christoph Hellwig
2018-09-20  7:02 ` merge dma_direct_ops and dma_noncoherent_ops v3 Christoph Hellwig

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