From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25B6FC43387 for ; Sun, 16 Dec 2018 02:15:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EBA8B2084D for ; Sun, 16 Dec 2018 02:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729761AbeLPCPl (ORCPT ); Sat, 15 Dec 2018 21:15:41 -0500 Received: from eddie.linux-mips.org ([148.251.95.138]:51210 "EHLO cvs.linux-mips.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727227AbeLPCPl (ORCPT ); Sat, 15 Dec 2018 21:15:41 -0500 Received: (from localhost user: 'macro', uid#1010) by eddie.linux-mips.org with ESMTP id S23992922AbeLPCPi4P1nj (ORCPT ); Sun, 16 Dec 2018 03:15:38 +0100 Date: Sun, 16 Dec 2018 02:15:38 +0000 (GMT) From: "Maciej W. Rozycki" To: Rich Felker cc: Andy Lutomirski , Linux MIPS Mailing List , LKML , Paul Burton , David Daney , Ralf Baechle , Paul Burton , James Hogan Subject: Re: Fixing MIPS delay slot emulation weakness? In-Reply-To: <20181215225009.GB23599@brightrain.aerifal.cx> Message-ID: References: <20181215225009.GB23599@brightrain.aerifal.cx> User-Agent: Alpine 2.21 (LFD 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 15 Dec 2018, Rich Felker wrote: > > A possibly nicer way to accomplish more or less the same thing would > > be to allocate the area with _install_special_mapping() and arrange to > > keep a reference to the struct page around. > > > > The really nice but less compatible fix would be to let processes or > > even the whole system opt out by promising not to put anything in FPU > > branch delay slots, of course. > > As I noted on Twitter when Mudge brought this topic back up, there's a > much more compatible, elegant, and safe fix possible that does not > involve any W+X memory. Emulate the delay slot in kernel-space. This > is trivial to do safely for pretty much everything but loads/stores. I think "trivial" is an understatement, you at least need to decode the delay-slot instruction enough to tell privileged and user instructions apart and send SIGILL where appropriate. Some user instructions send exceptions too and you need to handle them accordingly. OTOH, for things like ADDIUPC you need to interpret the instruction anyway, as the value of the PC used for calculation will be wrong except in the original location. > For loads/stores, where you want them to execute with user privilege > level, what you do is compute the effective address in kernel-space, > then return to a fixed instruction in the vdso page that performs a > generic load/store using the register the kernel put the effective > address result in, then restores registers off the stack and jumps to > the branch destination. What about all the odd and especially vendor-specific load/store instructions like ASET, SAA or SWAPW? Would we need to have all the possible encodings provided in the VDSO? Maciej