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From: "Maciej W. Rozycki" <>
To: Christoph Hellwig <>
	Shawn Anastasio <>,
	Michael Ellerman <>,
	Russell King <>,
	Catalin Marinas <>,
	Will Deacon <>,
	Robin Murphy <>,
	Paul Burton <>,
	James Hogan <>,,,,
Subject: Re: [PATCH 2/2] MIPS: remove support for DMA_ATTR_WRITE_COMBINE
Date: Wed, 18 Sep 2019 20:50:01 +0100 (BST)	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On Wed, 7 Aug 2019, Christoph Hellwig wrote:

> Mips uses the KSEG1 kernel memory segment to map dma coherent
> allocations for non-coherent devices as uncacheable, and does not have
> any kind of special support for DMA_ATTR_WRITE_COMBINE in the allocation
> path.  Thus supporting DMA_ATTR_WRITE_COMBINE in dma_mmap_attrs will
> lead to multiple mappings with different caching attributes.

 FYI, AFAIK _CACHE_UNCACHED_ACCELERATED (where supported) is effectively 
write-combine.  Though IIUC someone would have to wire it in first.


  reply	other threads:[~2019-09-18 19:50 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-07  6:16 fix default dma_mmap_* pgprot v3 Christoph Hellwig
2019-08-07  6:16 ` [PATCH 1/2] dma-mapping: fix page attributes for dma_mmap_* Christoph Hellwig
2019-08-07  6:16 ` [PATCH 2/2] MIPS: remove support for DMA_ATTR_WRITE_COMBINE Christoph Hellwig
2019-09-18 19:50   ` Maciej W. Rozycki [this message]
  -- strict thread matches above, loose matches on Subject: below --
2019-08-05  8:01 fix default dma_mmap_* pgprot v2 Christoph Hellwig
2019-08-05  8:01 ` [PATCH 2/2] MIPS: remove support for DMA_ATTR_WRITE_COMBINE Christoph Hellwig
2019-08-05  8:06   ` Sergei Shtylyov

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